ADSP-TS202S Datasheet, PDF(26/40 Page) Analog Devices

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

ADSP-TS202S Datasheet, PDF (26/40 Pages) Analog Devices – TigerSHARC Embedded Processor

◁

ADSP-TS202S

Table 22. AC Signal Specifications (Continued)

(all values in this table are in nanoseconds)

Name

Description

Preliminary Technical Data

DS2â06

SCLKRAT2â06

ENEDREG6

STRAP SYS7,8

JTAG SYS9

Static pins â must be constant

Static pins â must be connected to VSS â

Strap pins

1.5 0.5 â

SCLK

JTAG system pins

1.5 0.5 4.0 1.0 â

TCK

1 The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The

apparent driver overlap, due to output disables being larger than output enables, is not actual.

2 For input specifications on FLAG3â0 pins, see Table 17.

3 These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.

4 For additional requirement details, see Reset and Booting on page 9.

5 Reference clock depends on function.

6 These pins may change only during reset; recommend connecting it to VDD_IO/VSS.

7 STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, and L3BCMPO.

8 Specifications applicable during reset only.

9 JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3-0, DMAR3-0, HBR, BOFF, MS1-0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, BM, EMU, SDA10,

IOEN, BUSLOCK, TMR0E, DATA63-0, ADDR31-0, RD, WRL, WRH, BRST, MSSD3-0, RAS, CAS, SDWE, HBG, BR7-0, FLAG3-0, L0DATOP3-0, L0DATON3-0,

L1DATOP3-0, L1DATON3-0, L2DATOP3-0, L2DATON3-0, L3DATOP3-0, L3DATON3-0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP,

L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3-0, L0DATIN3-0, L1DATIP3-0, L1DATIN3-0, L2DATIP3-0, L2DATIN3-0,

L3DATIP3-0, L3DATIN3-0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO, L2ACKO, L3ACKO,

ACK, CPA, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2-0, CTRL_IMPD1-0, SCLKRAT2-0, DS2-0, ENEDREG.

REFERENCE

CLOCK

INPUT

SIGNAL

OUTPUT

SIGNAL

THREE-

STATE

1.25V

tSCLK OR tTCK

1.25V

INPUT

SETUP

INPUT

HOLD

OUTPUT

VALID

1.25V

OUTPUT

HOLD

OUTPUT

DISABLE

OUTPUT

ENABLE

Figure 11. General AC Parameters Timing

Rev. PrB | Page 26 of 40 | December 2003

▷