ADSP-TS202S Datasheet, PDF (35/40 Pages) Analog Devices – TigerSHARC Embedded Processor

Preliminary Technical Data
STRENGTH 4
25
(V_{DD_IO} = 2.5V)
20
15
10
RISE TIME_PRELIMINARY
y = 0.1071x + 0.9877
5
FALL TIME
y = 0.0798x + 1.0743
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE – pF
Figure 38. Typical Output Rise and Fall Time (10%–90%, V_{DD_IO} = 2.5 V) vs.
Load Capacitance at Strength 4
STRENGTH 5
25
(V_{DD_IO} = 2.5V)
20
15
10
RISE TIME ^PRELIMINARY
y = 0.1001x + 0.7763
5
FALL TIME
y = 0.0793x + 0.8691
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE – pF
Figure 39. Typical Output Rise and Fall Time (10%–90%, V_{DD_IO} = 2.5 V) vs.
Load Capacitance at Strength 5
STRENGTH 6
25
(V_{DD_IO} = 2.5V)
20
15
10
RISE TIM_PE^RELIMINARY
y = 0.0946x + 1.2187
5
FALL TIME
y = 0.0906x + 0.4597
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE – pF
Figure 40. Typical Output Rise and Fall Time (10%–90%, V_{DD_IO} = 2.5 V) vs.
Load Capacitance at Strength 6
ADSP-TS202S
STRENGTH 7
25
(V_{DD_IO} = 2.5V)
20
15
10
RISE TIMPE^RELIMINARY
y = 0.0907x + 1.0071
5
FALL TIME
y = 0.09x + 0.3134
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE – pF
Figure 41. Typical Output Rise and Fall Time (10%–90%, V_{DD_IO} = 2.5 V) vs.
Load Capacitance at Strength 7
15
STRENGTH 0–7
0
(V_{DD_IO} = 2.5V)
10
5
PRELIMINARY
1
2
3
4
5
6
7
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE – pF
Figure 42. Typical Output Valid (V_{DD_IO} = 2.5 V) vs. Load Capacitance at Max
Case Temperature and Strength 0–7¹
1 _{The line equations for the output valid versus load capacitance are:}
Strength 0: y = 0.0956x + 3.5662
Strength 1: y = 0.0523x + 3.2144
Strength 2: y = 0.0433x + 3.1319
Strength 3: y = 0.0391x + 2.9675
Strength 4: y = 0.0393x + 2.7653
Strength 5: y = 0.0373x + 2.6515
Strength 6: y = 0.0379x + 2.1206
Strength 7: y = 0.0399x + 1.9080
Rev. PrB | Page 35 of 40 | December 2003