ADAR7251_15 Datasheet, PDF (8/72 Pages) Analog Devices – 4-Channel, 16-Bit, Continuous Time Data Acquisition ADC

ADAR7251
Data Sheet
DIGITAL FILTER
Table 4.
Parameter
ADC DECIMATION FILTER
At fS = 1.2 MHz, Decimation
Ratio = 48
Pass Band
Pass-Band Droop
Stop Band
Stop-Band Attenuation
Group Delay
High-Pass Filter
Corner Frequency
Attenuation
Mode
At fS =1.2 MHz, decimation ratio = 48
Factor
Min Typ
−0.1 dB corner
At 600 kHz
0.166 × fS
0.666 × fS
−3 dB, programmable in eight steps
See Figure 24 in the Typical
Performance Characteristics section
200
−1.4
800
70
95
0.729
Max
Unit
kHz
dB
kHz
dB
μs
93.3
Hz
SPI PORT TIMING
DVDDx = 1.8 V, IOVDDx = 3.3 V, C LOAD = 22 pF, IOUT = ±1 mA.
Table 5.
Parameter
SPI PORT
tCCPH
tCCPL
fSPI_CLK
tCDS
tCDH
tCLS
tCLH
tCLPH
tCDH
tCOD
tCOTS
Description
See Figure 2
SPI_SCLK high
SPI_SCLK low
SPI_SCLK frequency
SPI_MOSI setup to SPI_SCLK rising
SPI_MOSI hold from SPI_SCLK rising
SPI_SS setup to SPI_SCLK rising
SPI_SS hold from SPI_SCLK rising
SPI_SS high
SPI_MISO hold from SPI_SCLK rising
SPI_MISO delay from SPI_SCLK falling
SPI_MISO tristate from SPI_SS rising
Limit at
Min
Typ
Max
Unit
50
ns
50
ns
10
MHz
10
ns
10
ns
10
ns
40
ns
10
ns
30
ns
30
ns
30
ns
SERIAL/PERIPHERAL PARALLEL INTERFACE (PPI) PORT TIMING
DVDDx = 1.8 V, IOVDDx = 3.3 V, C LOAD = 22 pF, IOUT = ±1 mA.
Table 6.
Limit at
Parameter
Description
Min Typ
Max Unit
INPUT MASTER CLOCK (MCLKIN)
Duty Cycle
MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS 40
60
%
fMCLKIN
MCLKIN frequency, PLL in MCLK mode
16
54
MHz
RESET
Reset Pulse, tRESET
RESET/PWDN held low
15
ns
PLL
Lock Time
1
ms
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