ADAR7251_15 Datasheet, PDF (22/72 Pages) Analog Devices – 4-Channel, 16-Bit, Continuous Time Data Acquisition ADC

ADAR7251
Table 10 describes the registers used to set the PLL.
Table 10. Registers Used to Set the PLL
Register Name
Description
0x000
CLK_CTRL Uses the PLL output for the internal
master clock, or bypasses the PLL
0x001
PLL_DEN
Sets the 16-bit denominator of the
fractional part (M)
0x002
PLL_NUM Sets the 16-bit numerator of the
fractional part (N)
0x003
PLL_CTRL
Sets the PLL mode, PLL enable, 4-bit
integer multiplier (R), and 4-bit integer
divider (X)
0x005
PLL_LOCK Checks the PLL lock status
The PLL can be used in either integer mode or fractional mode.
Integer Mode
Use integer mode when the input clock frequency is an integer
multiple of the PLL output frequency, governed by the following
equation:
fPLL = (R/X) × fIN
where fPLL = 115.2 MHz.
For example, if fIN = 19.2 MHz, then
(R/X) = fPLL (PLL Required Output)/fIN = 6
Therefore, R and X are set as follows: R = 6, and X = 1 (default).
To route the clock through the PLL, first set Register 0x000 to
0x0001.
In integer mode, the values set for N and M are ignored; leave
Register 0x001 and Register 0x002 at default.
Table 11 shows the name, function, and required settings for the
bits in Register 0x003.
Table 12. Required Register Writes for Fractional Mode
Register
Bits
Name
0x0001
[15:0]
PLL_DEN
0x0002
[15:0]
PLL_NUM
0x0003
[15:11]
PLL_INTEGER_DIV
[7:4]
PLL_INPUT_PRESCALE
1
PLL_TYPE
0
PLL_EN
Data Sheet
Table 11. Required Writes for Register 0x0003, Integer Mode
Bits Name
Function
Required
Setting
[15:11] PLL_INTEGER_DIV
Sets the R value 00110
[7:4] PLL_INPUT_PRESCALE Sets the X value 0001
1
PLL_TYPE
Sets the integer 0
mode for the PLL
0
PLL_EN
Enables the PLL 1
Set Register 0x003 to 0011000000000001, that is, 0x3011. To check
the status of the PLL, read Register 0x0005.
Fractional Mode
Fractional mode is used when the available clock input at
XIN/MCLKIN is a fractional multiple of the desired PLL output; it is
governed by the following equation:
fPLL = fIN × (R + (N/M))/X
For example, if XIN/MCLKIN = 16 MHz, the PLL output is
115.2 MHz.
To find the values of R, N, and M, use the following equation:
fPLL = fIN × (R + (N/M))/X
where:
fPLL = 115.2 MHz.
fIN = 16 MHz.
To find the values of R, N, M, and X, use the following equation:
(R + (N/M))/X = 115.2 MHz/16 MHz = 7.2 = 7 + (2/10)
Therefore, R, X, N and M can be set as follows: R = 7, X = 1
(default), N = 2, and M =10.
To route the clock through the PLL, first set Register 0x000 to
0x0001. See Table 12 for the required register settings while in
fractional mode.
Set Register 0x003 to 0011100000000001, that is, 0x3813. To check
the status of the PLL, read Register 0x005.
PLL Lock Acquisition
Register 0x005 is a read only register that indicates the PLL status.
After writing the PLL settings, it is recommended to read the PLL
lock status bit to ensure that the PLL is locked. A PLL_LOCK bit
value of 1 indicates that the PLL is locked.
Function
Sets the M value
Sets the N value
Sets the R value
Sets the X value
Sets the fractional mode
for the PLL
Enables the PLL
Required Setting
0000000000001010 (that is, 0x000A)
0000000000000010 (that is, 0x0002)
00111
0001
1
1
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