ADAR7251_15 Datasheet, PDF (53/72 Pages) Analog Devices – 4-Channel, 16-Bit, Continuous Time Data Acquisition ADC

Data Sheet
Bits Bit Name
4
LRCLK_POL
3
BCLK_POL
2
DATA_FMT
[1:0] TDM_MODE
Settings
0
1
0
1
0
1
00
01
10
11
Description
Frame Sync (FS_ADC) Polarity.
Negative Polarity.
Positive Polarity.
SCLK_ADC Polarity.
Negative Polarity.
Positive Polarity.
Serial Data Format.
Left Justified Format.
I2S Format—Data Delayed by 1 SCLK Period.
Channels per Frame and SCLK Cycles per Channel.
2 Channels, 16 Bits per Channel.
4 Channels, 16 Bits per Channel.
Reserved.
Reserved.
PARALLEL PORT CONTROL REGISTER
Address: 0x1C1, Reset: 0x0000, Name: PARALLEL_MODE
ADAR7251
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
Table 50. Bit Descriptions for PARALLEL_MODE
Bits Bit Name
Settings Description
2
PAR_NIBBLE
Enable Nibble Mode.
1 Byte Mode.
0 Nibble Mode.
1
PAR_ENDIAN
High Byte/Low Byte Order.
0 High Byte Goes Out First.
1 Low Byte Goes Out First.
0
PAR_CHANNELS
Number of Channels to be Output.
1 2 Channels.
0 4 Channels.
Reset
0x0
Access
RW
0x0
RW
0x0
RW
Rev. 0 | Page 53 of 72