ADSP-BF700 Datasheet, PDF (78/116 Pages) Analog Devices – Instruction set compatible with previous Blackfin products

ADSP-BF700/701/702/703/704/705/706/707
Debug Interface (JTAG Emulation Port) Timing
Table 48 and Figure 26 provide I/O timing, related to the debug interface (JTAG emulator port).
Table 48. JTAG Port Timing
V_{DD_EXT}
1.8 V Nominal
V_{DD_EXT}
3.3 V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t_TCK
JTG_TCK Period
20
20
ns
t_STAP
JTG_TDI, JTG_TMS Setup Before JTG_TCK High
5
4
ns
t_HTAP
JTG_TDI, JTG_TMS Hold After JTG_TCK High
4
4
ns
t_SSYS
System Inputs Setup Before JTG_TCK High¹
4
4
ns
t_HSYS
System Inputs Hold After JTG_TCK High¹
4
4
ns
t_TRSTW
JTG_TRST Pulse Width (Measured in JTG_TCK Cycles)² 4
4
t_TCK
Switching Characteristics
t_DTDO
JTG_TDO Delay From JTG_TCK Low
16.5
14.5
ns
t_DSYS
System Outputs Delay After JTG_TCK Low³
18
16.5
ns
t_DTMS
TMS Delay After TCK High in SWD Mode
3.5
16.5
3.5
14.5
ns
1 _{System inputs = DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, PA_xx, PB_xx, PC_xx, SYS_BMODEx, SYS_HWRST, SYS_FAULT, ï€} 
SYS_NMI, TWI0_SCL, TWI0_SDA, and SYS_EXTWAKE.
2 _{50 MHz maximum.}
3 _{System outputs = DMC0_Axx, DMC0_BAx, DMC0_CAS, DMC0_CK, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQxx, DMC0_LDM, DMC0_LDQS, DMC0_LDQS,}
DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, DMC0_WE, PA_xx, PB_xx, PC_xx, SYS_CLKOUT, SYS_FAULT, SYS_RESOUT, and SYS_NMI.
JTG_TCK
JTG_TMS
JTG_TDI
JTG_TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t_TCK
t_STAP
t_DTDO
t_SSYS
t_DSYS
t_HTAP
t_HSYS
Figure 26. JTAG Port Timing
Rev. A | Page 78 of 116 | September 2015