ADSP-BF700 Datasheet, PDF (19/116 Pages) Analog Devices – Instruction set compatible with previous Blackfin products

ADSP-BF700/701/702/703/704/705/706/707
Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued)
Port Name
HADC_VREFN
HADC_VREFP
MSI_CD
MSI_CLK
MSI_CMD
MSI_Dn
MSI_INT
Px_nn
RTC_CLKIN
RTC_XTAL
SMC_ABEn
SMC_AMSn
SMC_AOE
SMC_ARDY
SMC_ARE
SMC_AWE
SMC_Ann
SMC_Dnn
SPI_CLK
SPI_D2
SPI_D3
SPI_MISO
SPI_MOSI
SPI_RDY
SPI_SELn
SPI_SS
SPT_ACLK
SPT_AD0
SPT_AD1
SPT_AFS
SPT_ATDV
Direction
Input
Input
Input
Output
I/O
I/O
Input
I/O
Input
Output
Output
Output
Output
Input
Output
Output
Output
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Output
Input
I/O
I/O
I/O
I/O
Output
Description
Ground Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
External Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
Card Detect. Connects to a pull-up resistor and to the card detect output of an SD socket.
Clock. The clock signal applied to the connected device from the MSI.
Command. Used to send commands to and receive responses from the connected device.
Data n. Bidirectional data bus.
eSDIO Interrupt Input. Used only for eSDIO. Connects to an eSDIO card's interrupt output. An
interrupt may be sampled even when the MSI clock to the card is switched off.
Position n. General purpose input/output. See the GP Ports chapter of the HRM for programming
information.
Crystal input/external oscillator connection. Connect to an external clock source or crystal.
Crystal output. Drives an external crystal. Must be left unconnected if an external clock is driving
RTC_CLKIN.
Byte Enable n. Indicate whether the lower or upper byte of a memory is being accessed. When an
asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1b=0 and SMC_ABE0b=1.
When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1b=1 and SMC_
ABE0b=0.
Memory Select n. Typically connects to the chip select of a memory device.
Output Enable. Asserts at the beginning of the setup period of a read access.
Asynchronous Ready. Flow control signal used by memory devices to indicate to the SMC when
further transactions may proceed.
Read Enable. Asserts at the beginning of a read access.
Write Enable. Asserts for the duration of a write access period.
Address n. Address bus.
Data n. Bidirectional data bus.
Clock. Input in slave mode, output in master mode.
Data 2. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled.
Data 3. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled.
Master In, Slave Out. Used to transfer serial data. Operates in the same direction as SPI_MOSI in Dual
and Quad modes. Open-drain when ODM mode is enabled.
Master Out, Slave In. Used to transfer serial data. Operates in the same direction as SPI_MISO in Dual
and Quad modes. Open-drain when ODM mode is enabled.
Ready. Optional flow signal. Output in slave mode, input in master mode.
Slave Select Output n. Used in Master mode to enable the desired slave.
Slave Select Input. Slave mode - Acts as the slave select input. Master mode- Optionally serves as an
error detection input for the SPI when there are multiple masters.
Channel A Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can
be either internally or externally generated.
Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multichannel transmit mode. It is asserted during enabled slots.
Rev. A | Page 19 of 116 | September 2015