ADSP-BF700 Datasheet, PDF (20/116 Pages) Analog Devices – Instruction set compatible with previous Blackfin products

ADSP-BF700/701/702/703/704/705/706/707
Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued)
Port Name
SPT_BCLK
SPT_BD0
SPT_BD1
SPT_BFS
SPT_BTDV
SYS_BMODEn
SYS_CLKIN
SYS_CLKOUT
SYS_EXTWAKE
SYS_FAULT
SYS_HWRST
SYS_NMI
SYS_RESOUT
SYS_WAKEn
SYS_XTAL
JTG_SWCLK
JTG_SWDIO
JTG_SWO
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
TM_ACIn
TM_ACLKn
TM_CLK
TM_TMRn
TRACE_CLK
TRACE_Dnn
TWI_SCL
TWI_SDA
UART_CTS
UART_RTS
UART_RX
UART_TX
USB_CLKIN
Direction
I/O
I/O
I/O
I/O
Output
Input
Input
Output
Output
I/O
Input
Input
Output
Input
Output
I/O
I/O
Output
Input
Input
Output
Input
Input
Input
Input
Input
I/O
Output
Output
I/O
I/O
Input
Output
Input
Output
Input
Description
Channel B Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can
be either internally or externally generated.
Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multi-channel transmit mode. It is asserted during enabled slots.
Boot Mode Control n. Selects the boot mode of the processor.
Clock/Crystal Input. Connect to an external clock source or crystal.
Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter
of the HRM for more details.
External Wake Control. Drives low during hibernate and high all other times. Typically connected to
the enable input of the voltage regulator controlling the VDD_INT supply.
Active-Low Fault Output. Indicates internal faults or senses external faults depending on the
operating mode.
Processor Hardware Reset Control. Resets the device when asserted.
Non-maskable Interrupt. See the processor hardware and programming references for more details.
Reset Output. Indicates that the device is in the reset or hibernate state.
Power Saving Mode Wakeup n. Wake-up source input for deep sleep and/or hibernate mode.
Crystal Output. Drives an external crystal. Must be left unconnected if an external clock is driving
CLKIN.
Serial Wire Clock. Clocks data into and out of the target during debug.
Serial Wire DIO. Sends and receives serial data to and from the target during debug.
Serial Wire Out. Provides trace data to the emulator.
JTAG Clock. JTAG test access port clock.
JTAG Serial Data In. JTAG test access port data input.
JTAG Serial Data Out. JTAG test access port data output.
JTAG Mode Select. JTAG test access port mode select.
JTAG Reset. JTAG test access port reset.
Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.
Alternate Clock n. Provides an additional time base for use by an individual timer.
Clock. Provides an additional global time base for use by all the GP timers.
Timer n. The main input/output signal for each timer.
Trace Clock. Clock output.
Trace Data n. Unidirectional data bus.
Serial Clock. Clock output when master, clock input when slave.
Serial Data. Receives or transmits data.
Clear to Send. Flow control signal.
Request to Send. Flow control signal.
Receive. Receive input. Typically connects to a transceiver that meets the electrical requirements of
the device being communicated with.
Transmit. Transmit output. Typically connects to a transceiver that meets the electrical requirements
of the device being communicated with.
Clock/Crystal Input. This clock input is multiplied by a PLL to form the USB clock. See data sheet
specifications for frequency/tolerance information.
Rev. A | Page 20 of 116 | September 2015