ADSP-BF700 Datasheet, PDF (38/116 Pages) Analog Devices – Instruction set compatible with previous Blackfin products

ADSP-BF700/701/702/703/704/705/706/707
ADSP-BF70x DESIGNER QUICK REFERENCE
Table 15 provides a quick reference summary of pin related
information for circuit board design. The columns in this table
provide the following information:
• Signal Name: The Signal Name column in the table
includes the signal name for every pin and (where applica-
ble) the GPIO multiplexed pin function for every pin.
• Pin Type: The Type column in the table identifies the I/O
type or supply type of the pin. The abbreviations used in
this column are na (none), I/O (input/output), a (analog), s
(supply), and g (ground).
• Driver Type: The Driver Type column in the table identi-
fies the driver type used by the pin. The driver types are
defined in the output drive currents section of this data
sheet.
• Internal Termination: The Int Term column in the table
specifies the termination present when the processor is not
in the reset or hibernate state. The abbreviations used in
this column are wk (weak keeper, weakly retains previous
value driven on the pin), pu (pull-up), or pd (pull-down).
• Reset Termination: The Reset Term column in the table
specifies the termination present when the processor is in
the reset state. The abbreviations used in this column are
wk (weak keeper, weakly retains previous value driven on
the pin), pu (pull-up), or pd (pull-down).
• Reset Drive: The Reset Drive column in the table specifies
the active drive on the signal when the processor is in the
reset state.
• Hibernate Termination: The Hiber Term column in the
table specifies the termination present when the processor
is in the hibernate state. The abbreviations used in this col-
umn are wk (weak keeper, weakly retains previous value
driven on the pin), pu (pull-up), or pd (pull-down).
• Hibernate Drive: The Hiber Drive column in the table
specifies the active drive on the signal when the processor is
in the hibernate state.
• Power Domain: The Power Domain column in the table
specifies the power supply domain in which the signal
resides.
• Description and Notes: The Description and Notes column
in the table identifies any special requirements or charac-
teristics for the signal. If no special requirements are listed
the signal may be left unconnected if it is not used. Also, for
multiplexed general-purpose I/O pins, this column identi-
fies the functions available on the pin.
If an external pull-up or pull-down resistor is required for any
signal, 100 kΩ is the maximum value that can be used unless
otherwise noted.
Note that for Port A, Port B, and Port C (PA_00 to PC_14),
when SYS_HWRST is low, these pads are three-state. After 
SYS_HWRST is released, but before code execution begins,
these pins are internally pulled up. Subsequently, the state
depends on the input enable and output enable which are
controlled by software.
Software control of internal pull-ups works according to the
following settings in the PADS_PCFG0 register. When 
PADS_PCFG0 = 0: For PA_15:PA_00, PB_15:PB_00, and 
PC_14:PC_00, the internal pull-up is enabled when both the
input enable and output enable of a particular pin are 
deasserted. When PADS_PCFG0 = 1: For PA_15:PA_00, 
PB_15:PB_00, and PC_14:PC_00, the internal pull-up is
enabled as long as the output enable of a particular pin is 
deasserted.
There are some exceptions to this scheme:
• Internal pull-ups are always disabled if MSI mode is
selected for that signal.
• The following signals enabled the internal pull-down when
the output enable is de-asserted: SMC0_AMS[1:0], 
SMC0_ARE, SMC0_AWE, SMC0_AOE, SMC0_ARDY,
SPI0_SEL[6:1], SPI1_SEL[4:1], and SPI2_SEL[3:1].
Table 15. ADSP-BF70x Designer Quick Reference
Signal Name Type
DMC0_A00 I/O
Driver
Type
B
Int 
Term
none
Reset
Term
none
DMC0_A01 I/O
B
none none
DMC0_A02 I/O
B
none none
DMC0_A03 I/O
B
none none
DMC0_A04 I/O
B
none none
DMC0_A05 I/O
B
none none
Reset
Drive
none
none
none
none
none
none
Hiber
Term
none
none
none
none
none
none
Hiber
Drive
none
none
none
none
none
none
Power
Domain
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Description
and Notes
Desc: DMC0 Address 0
Notes: No notes.
Desc: DMC0 Address 1
Notes: No notes.
Desc: DMC0 Address 2
Notes: No notes.
Desc: DMC0 Address 3
Notes: No notes.
Desc: DMC0 Address 4
Notes: No notes.
Desc: DMC0 Address 5
Notes: No notes.
Rev. A | Page 38 of 116 | September 2015