AD9516-4 Datasheet, PDF (76/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 1.6 GHz VCO

AD9516-4
Reg.
Addr
(Hex)
198
Bit(s)
<1>
Name
Divider 2 Direct to Output
198 <0> Divider 2 DCCOFF
Description
Connect OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.
<1> = 0; OUT4 and OUT5 are connected to Divider 2.
<1> = 1:
If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT4 and OUT5.
If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT4 and OUT5.
If 0x1E1<1:0> = 01b, there is no effect.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
Table 58. LVDS/CMOS Channel Dividers
Reg.
Addr
(Hex) Bit(s) Name
Description
199 <7:4> Low Cycles Divider 3.1
Number of clock cycles of 3.1 divider input during which 3.1 output stays low.
199 <3:0> High Cycles Divider 3.1
Number of clock cycles of 3.1 divider input during which 3.1 output stays high.
19A <7:4> Phase Offset Divider 3.2 Refer to LVDSCMOS channel divider function description.
19A <3:0> Phase Offset Divider 3.1 Refer to LVDSCMOS channel divider function description.
19B <7:4> Low Cycles Divider 3.2
Number of clock cycles of 3.2 divider input during which 3.2 output stays low.
19B <3:0> High Cycles Divider 3.2
Number of clock cycles of 3.2 divider input during which 3.2 output stays high.
19C <5> Bypass Divider 3.2
19C <4> Bypass Divider 3.1
19C <3> Divider 3 Nosync
19C <2> Divider 3 Force High
19C <1> Start High Divider 3.2
19C <0> Start High Divider 3.1
19D <0> Divider 3 DCCOFF
19E <7:4> Low Cycles Divider 4.1
Bypass (and power-down) 3.2 divider logic, route clock to 3.2 output.
<5> = 0; do not bypass.
<5> = 1; bypass.
Bypass (and power-down) 3.1 divider logic, route clock to 3.1 output.
<4> = 0; do not bypass.
<4> = 1; bypass.
Nosync.
<3> = 0; obey chip-level SYNC signal.
<3> = 1; ignore chip-level SYNC signal.
Force Divider 3 output high. Requires that nosync also be set.
<2> = 0; force low.
<2> = 1; force high.
Divider 3.2 start high/low.
<1> = 0; start low.
<1> = 1; start high.
Divider 3.1 start high/low.
<0> = 0; start low.
<0> = 1; start high.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
Number of clock cycles of divider 4.1 input during which 4.1 output stays low.
19E <3:0> High Cycles Divider 4.1
Number of clock cycles of 4.1 divider input during which 4.1 output stays high.
19F <7:4> Phase Offset Divider 4.2 Refer to LVDSCMOS channel divider function description.
19F <3:0> Phase Offset Divider 4.1 Refer to LVDSCMOS channel divider function description.
1A0 <7:4> Low Cycles Divider 4.2
Number of clock cycles of 4.2 divider input during which 4.2 output stays low.
1A0 <3:0> High Cycles Divider 4.2
Number of clock cycles of 4.2 divider input during which 4.2 output stays high.
Rev. 0 | Page 76 of 84