AD9516-4 Datasheet, PDF (14/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 1.6 GHz VCO

AD9516-4
POWER DISSIPATION
Table 17.
Parameter
POWER DISSIPATION, CHIP
Power-On Default
Full Operation; CMOS Outputs at 229 MHz
Full Operation; LVDS Outputs at 200 MHz
PD Power-Down
PD Power-Down, Maximum Sleep
VCP Supply
POWER DELTAS, INDIVIDUAL FUNCTIONS
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
VCO
PLL
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
LVPECL Driver
LVDS Channel (Divider Plus Output Driver)
LVDS Driver
CMOS Channel (Divider Plus Output Driver)
CMOS Driver (Second in Pair)
CMOS Driver (First in Second Pair)
Fine Delay Block
Min Typ Max Unit Test Conditions/Comments
1.0 1.2 W
No clock; no programming; default register values;
does not include power dissipated in external resistors
1.6 2.2 W
PLL on; internal VCO = 1625 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs @ 406 MHz;
eight CMOS outputs (10 pF load) @ 203 MHz; all fine
delay on, maximum current; does not include power
dissipated in external resistors
1.6 2.3 W
PLL on; internal VCO = 1625 MHz, VCO divider = 2;
all channel dividers on; six LVPECL outputs @ 406 MHz;
four LVDS outputs @ 203 MHz; all fine delay on,
maximum current; does not include power dissipated
in external resistors
75 185 mW PD _{pin pulled low; does not include power dissipated}
in terminations
31
mW PD _{pin pulled low; PLL power-down 0x10<1:0> = 01b;}
SYNC power-down 0x230<2> = 1b; REF for distribution
power-down 0x230<1> = 1b
1.5
mW PLL operating; typical closed loop configuration
Power delta when a function is enabled/disabled
30
mW VCO divider not used
20
mW All references off to differential reference enabled
4
mW All references off to REF1 or REF2 enabled; differential
reference not enabled
70
mW CLK input selected to VCO selected
75
mW PLL off to PLL on, normal operation; no reference enabled
30
mW Divider bypassed to divide-by-2 to 32
160
mW No LVPECL output on to one LVPECL output on
90
mW Second LVPECL output turned on, same channel
120
mW No LVDS output on to one LVDS output on
50
mW Second LVDS output turned on, same channel
100
mW Static; no CMOS output on to one CMOS output on
0
mW Static; second CMOS output, same pair, turned on
30
mW Static; first output, second pair, turned on
50
mW Delay block off to delay block enabled; maximum
current setting
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