AD9516-4 Datasheet, PDF (40/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 1.6 GHz VCO

AD9516-4
REF_SEL
VS GND
RSET
REFMON
CPRSET VCP
REFIN (REF1)
REFIN (REF2)
BYPASS
REF1
REF2
REFERENCE
SWITCHOVER
STATUS
STATUS
LOW DROPOUT
REGULATOR (LDO)
DISTRIBUTION
REFERENCE
R
DIVIDER
PROGRAMMABLE
R DELAY
N DIVIDER
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
LOCK
DETECT
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
LF
CLK
CLK
VCO
VCO STATUS
DIVIDE BY
0
2, 3, 4, 5, OR 6
1
10
Figure 52. Reference and VCO Status Monitors
LD
CP
STATUS
VCO Calibration
The AD9516 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. The VCO calibration
is controlled by a calibration controller running off of a divided
REFIN clock. The calibration requires that the PLL be set up
properly to lock the PLL loop and that the REFIN clock be
present. During the first initialization after a power-up or a
reset of the AD9516, a VCO calibration sequence is initiated by
setting 0x18<0> = 1b. This can be done as part of the initial
setup, before executing update registers (0x232<0> = 1b).
Subsequent to the initial setup, a VCO calibration sequence is
initiated by resetting 0x18<0> = 0b, executing an update registers
operation, setting 0x18<0> = 1b, and executing another update
registers operation. A readback bit (0x1F<6>) indicates when a
VCO calibration is finished by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration is:
• Program the PLL registers to the proper values for the PLL loop.
• For initial setting of registers after a power-up or reset,
initiate VCO calibration by setting 0x18<0> = 1. Subsequently,
whenever a calibration is desired, set 0x18<0> = 0b, update
registers, and set 0x18<0> = 1b, update registers.
• A SYNC operation is initiated internally, causing the outputs
to go to a static state determined by normal SYNC function
operation.
• VCO calibrates to desired setting for requested VCO frequency.
• Internally, the SYNC signal is released, allowing outputs to
continue clocking.
• PLL loop is closed.
• PLL locks.
A SYNC is executed during the VCO calibration; therefore, the
outputs of the AD9516 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 53
(0x18<2:1>).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
fCAL_CLOCK = fREFIN/(R × cal_div)
where:
fREFIN is the frequency of the REFIN signal.
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(0x18<2:1>).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
Table 29. Example Time to Complete a VCO Calibration with
Different fREFIN Frequencies
fREFIN (MHz)
100
10
10
R Divider
1
10
100
PFD
100 MHz
1 MHz
100 kHz
Time to Calibrate VCO
88 μs
8.8 ms
88 ms
Rev. 0 | Page 40 of 84