AD9516-4 Datasheet, PDF (23/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 1.6 GHz VCO

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Figure 31. Phase Noise (Additive) LVPECL @ 245.76 MHz, Divide-by-1
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Figure 32. Phase Noise (Additive) LVPECL @ 200 MHz, Divide-by-5
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Figure 33. Phase Noise (Additive) LVPECL @ 1600 MHz, Divide-by-1
AD9516-4
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Figure 34. Phase Noise (Additive) LVDS @ 200 MHz, Divide-by-1
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Figure 35. Phase Noise (Additive) LVDS @ 800 MHz, Divide-by-2
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Figure 36. Phase Noise (Additive) CMOS @ 50 MHz, Divide-by-20
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