AD9516-4 Datasheet, PDF (6/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 1.6 GHz VCO

AD9516-4
Parameter
PLL DIGITAL LOCK DETECT WINDOW²
Min Typ Max
Required to Lock (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
3.5
High Range (ABP 1.3 ns, 2.9 ns)
7.5
High Range (ABP 6 ns)
3.5
To Unlock After Lock (Hysteresis)²
Low Range (ABP 1.3 ns, 2.9 ns)
7
High Range (ABP 1.3 ns, 2.9 ns)
15
High Range (ABP 6 ns)
11
Unit Test Conditions/Comments
Signal available at LD, STATUS, and REFMON pins
when selected by appropriate register settings
Selected by 0x17<1:0> and 0x18<4>
ns
0x17<1:0> = 00b, 01b,11b; 0x18<4> = 1b
ns
0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b
ns
0x17<1:0> = 10b; 0x18<4> = 0b
ns
0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 1b
ns
0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b
ns
0x17<1:0> = 10b; 0x18<4> = 0b
1 _{REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.}
2 _{For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.}
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Input Sensitivity, Differential
Min Typ Max Unit
0¹
2.4 GHz
0¹
1.6 GHz
150
mV p-p
Input Level, Differential
2
V p-p
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
1.3 1.57 1.8 V
1.3
1.8 V
150
mV p-p
3.9 4.7 5.7 kΩ
2
pF
1 _{Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.}
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed)
Measured at 2.4 GHz. Jitter performance is improved
with slew rates > 1 V/ns
Larger voltage swings may turn on the protection
diodes and can degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Output Frequency, Maximum
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
LVDS CLOCK OUTPUTS
OUT6, OUT7, OUT8, OUT9
Output Frequency
Differential Output Voltage (VOD)
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
Short-Circuit Current (ISA, ISB)
Min
Typ
Max
Unit Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Differential (OUT, OUT)
2950
MHz Using direct to output; see Figure 25
VS − 1.12 VS − 0.98 VS − 0.84 V
VS − 2.03 VS − 1.77 VS − 1.49 V
550
790
980
mV
Differential termination 100 Ω @ 3.5 mA
Differential (OUT, OUT)
800
MHz See Figure 26
247
360
454
mV
25
mV
1.125
1.24
1.375
V
25
mV
14
24
mA Output shorted to GND
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