ADSP-BF542_15 Datasheet, PDF (75/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
HOSTDP A/C Timing-Host Write Cycle
Table 55 and Figure 47 describe the HOSTDP A/C host write
cycle timing requirements.
Table 55. Host Write Cycle Timing Requirements
Parameter
Min
Max
Unit
Timing Requirements
t_SADWRL HOST_ADDR/HOST_CE Setup Before HOST_WR Falling Edge
4
ns
t_HADWRH HOST_ADDR/HOST_CE Hold After HOST_WR Rising Edge
2.5
ns
t_WRWL
HOST_WR Pulse Width Low (ACK Mode)
t_DRDYWRL + t_RDYPRD + t_DWRHRDY
ns
HOST_WR Pulse Width Low (INT Mode)
1.5 × t_SCLK + 8.7
ns
t_WRWH
HOST_WR Pulse Width High or Time Between HOST_WR Rising Edge 2 × t_SCLK
ns
and HOST_RD Falling Edge
t_DWRHRDY HOST_WR Rising Edge Delay After HOST_ACK Rising Edge (ACK Mode) 0
ns
t_HDATWH HOST_D15–0 Hold After HOST_WR Rising Edge
2.5
ns
t_SDATWH HOST_D15–0 Setup Before HOST_WR Rising Edge
3.5
ns
Switching Characteristics
t_DRDYWRL HOST_ACK Falling Edge After HOST_CE Asserted (ACK Mode)
11.25
ns
t_RDYPWR HOST_ACK Low Pulse-Width for Write Access (ACK Mode)
NM¹
ns
1 _{NM (not measured)—This parameter is based on tSCLK. It is not measured because the number of SCLK cycles for which HOST_ACK remains low depends on the Host DMA}
FIFO status. This is system design dependent.
HOST_ADDR
HOST_CE
HOST_WR
HOST_DATA
HOST_ACK
t_SADWRL
t_WRWL
t_HADWRH
t_WRWH
t_SDATWH
t_HDATWH
t_DRDYWRL
t_RDYPWR
t_DWRHRDY
In Figure 47, HOST_DATA is HOST_D0–D15.
Figure 47. HOSTDP A/C- Host Write Cycle
Rev. E | Page 75 of 102 | March 2014