ADSP-BF542_15 Datasheet, PDF (14/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
The USB clock (USB_XI) is provided through a dedicated exter-
nal crystal or crystal oscillator. See Table 62 for related timing
requirements. If using a fundamental mode crystal to provide
the USB clock, connect the crystal between USB_XI and
USB_XO with a circuit similar to that shown in Figure 7. Use a
parallel-resonant, fundamental mode, microprocessor-grade
crystal. If a third-overtone crystal is used, follow the circuit
guidelines outlined in Clock Signals on Page 17 for third-over-
tone crystals.
The USB On-the-Go dual-role device controller includes a
Phase Locked Loop with programmable multipliers to generate
the necessary internal clocking frequency for USB. The multi-
plier value should be programmed based on the USB_XI clock
frequency to achieve the necessary 480 MHz internal clock for
USB high speed operation. For example, for a USB_XI crystal
frequency of 24 MHz, the USB_PLLOSC_CTRL register should
be programmed with a multiplier value of 20 to generate a
480 MHz internal clock.
ATA/ATAPI-6 INTERFACE
The ATAPI interface connects to CD/DVD and HDD drives
and is ATAPI-6 compliant. The controller implements the
peripheral I/O mode, the multi-DMA mode, and the Ultra
DMA mode. The DMA modes enable faster data transfer and
reduced host management. The ATAPI controller supports
PIO, multi-DMA, and ultra DMA ATAPI accesses. Key features
include:
• Supports PIO modes 0, 1, 2, 3, 4
• Supports multiword DMA modes 0, 1, 2
• Supports ultra DMA modes 0, 1, 2, 3, 4, 5 (up to UDMA
100)
• Programmable timing for ATA interface unit
• Supports CompactFlash cards using true IDE mode
By default, the ATAPI_A0-2 address signals and the ATA-
PI_D0-15 data signals are shared on the asynchronous memory
interface with the asynchronous memory and NAND flash con-
trollers. The data and address signals can be remapped to GPIO
ports F and G, respectively, by setting PORTF_MUX[1:0] to
b#01.
KEYPAD INTERFACE
The keypad interface is a 16-pin interface module that is used to
detect the key pressed in a 8 × 8 (maximum) keypad matrix. The
size of the input keypad matrix is programmable. The interface
is capable of filtering the bounce on the input pins, which is
common in keypad applications. The width of the filtered
bounce is programmable. The module is capable of generating
an interrupt request to the core once it identifies that any key
has been pressed.
The interface supports a press-release-press mode and infra-
structure for a press-hold mode. The former mode identifies a
press, release and press of a key as two consecutive presses of the
same key, whereas the latter mode checks the input key’s state in
periodic intervals to determine the number of times the same
key is meant to be pressed. It is possible to detect when multiple
keys are pressed simultaneously and to provide limited key reso-
lution capability when this happens.
SECURE DIGITAL (SD)/SDIO CONTROLLER
The SD/SDIO controller is a serial interface that stores data at a
data rate of up to 10M bytes per second using a 4-bit data line.
The SD/SDIO controller supports the SD memory mode only.
The interface supports all the power modes and performs error
checking by CRC.
CODE SECURITY
An OTP/security system, consisting of a blend of hardware and
software, provides customers with a flexible and rich set of code
security features with Lockbox^® secure technology. Key features
include:
• OTP memory
• Unique chip ID
• Code authentication
• Secure mode of operation
The security scheme is based upon the concept of authentica-
tion of digital signatures using standards-based algorithms and
provides a secure processing environment in which to execute
code and protect assets. See Lockbox Secure Technology Dis-
claimer on Page 23.
MEDIA TRANSCEIVER MAC LAYER (MXVR)
The ADSP-BF549 Blackfin processors provide a media trans-
ceiver (MXVR) MAC layer, allowing the processor to be
connected directly to a MOST^{® 1} network through an FOT. See
Figure 5 on Page 15 for an example of a MXVR MOST
connection.
The MXVR is fully compatible with industry-standard stand-
alone MOST controller devices, supporting 22.579 Mbps or
24.576 Mbps data transfer. It offers faster lock times, greater jit-
ter immunity, and a sophisticated DMA scheme for data
transfers. The high speed internal interface to the core and L1
memory allows the full bandwidth of the network to be utilized.
The MXVR can operate as either the network master or as a net-
work slave.
The MXVR supports synchronous data, asynchronous packets,
and control messages using dedicated DMA channels that oper-
ate autonomously from the processor core moving data to and
from L1 and/or L2 memory. Synchronous data is transferred to
or from the synchronous data physical channels on the MOST
bus through eight programmable DMA channels. The synchro-
nous data DMA channels can operate in various modes
including modes that trigger DMA operation when data pat-
terns are detected in the receive data stream. Furthermore, two
DMA channels support asynchronous traffic, and two others
support control message traffic.
1 _{MOST is a registered trademark of Standard Microsystems, Corp.}
Rev. E | Page 14 of 102 | March 2014