ADSP-BF542_15 Datasheet, PDF (22/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly inte-
grate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware pack-
ages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZ-
Extender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZ-
Extender product. The link is found in the Product Download
area of the product web page.
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
• www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that per-
form popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices sup-
plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emu-
lator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set break-
points, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emu-
lators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see the Engineer-to-Engineer
Note “Analog Devices JTAG Emulation Technical Reference”
(EE-68) on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
MXVR BOARD LAYOUT GUIDELINES
The MXVR Loop Filter RC network is connected between the
MLF_P and MLF_M pins in the following manner:
Capacitors:
• C1: 0.047 μF (PPS type, 2% tolerance recommended)
• C2: 330 pF (PPS type, 2% tolerance recommended)
Resistor:
• R1: 330 Ω (1% tolerance)
The RC network should be located physically close to the
MLF_P and MLF_M pins on the board.
The RC network should be shielded using GND_MP traces.
Avoid routing other switching signals near the RC network to
avoid crosstalk.
MXI driven with external clock oscillator IC:
• MXI should be driven with the clock output of a clock
oscillator IC running at a frequency of 49.152 MHz or
45.1584 MHz.
• MXO should be left unconnected.
• Avoid routing other switching signals near the oscillator
and clock output trace to avoid crosstalk. When not possi-
ble, shield traces with ground.
MXI/MXO with external crystal:
• The crystal must be a fundamental mode crystal running at
a frequency of 49.152 MHz or 45.1584 MHz.
• The crystal and load capacitors should be placed physically
close to the MXI and MXO pins on the board.
• Board trace capacitance on each lead should not be more
than 3 pF.
• Trace capacitance plus load capacitance should equal the
load capacitance specification for the crystal.
• Avoid routing other switching signals near the crystal and
components to avoid crosstalk. When not possible, shield
traces and components with ground.
V_DDMP/GND_MP—MXVR PLL power domain:
• Route V_DDMP and GND_MP with wide traces or as isolated
power planes.
• Drive V_DDMP to same level as V_DDINT.
• Place a ferrite bead between the V_DDINT power plane and the
V_DDMP pin for noise isolation.
• Locally bypass V_DDMP with 0.1 μF and 0.01 μF decoupling
capacitors to GND_MP.
• Avoid routing switching signals near to V_DDMP and GND_MP
traces to avoid crosstalk.
Rev. E | Page 22 of 102 | March 2014