ADSP-BF542_15 Datasheet, PDF (3/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
GENERAL DESCRIPTION
The ADSP-BF54x Blackfin^® processors are members of the
Blackfin family of products, incorporating the Analog Devices/
Intel Micro Signal Architecture (MSA). Blackfin processors
combine a dual-MAC state-of-the-art signal processing engine,
the advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
Specific performance, memory configurations, and features of
ADSP-BF54x Blackfin processors are shown in Table 1.
Table 1. ADSP-BF54x Processor Features
Processor Features
Lockbox^{® 1}code security
11111
128-bit AES/ ARC4 data encryption
11111
SD/SDIO controller
111–1
Pixel compositor
11111
18- or 24-bit EPPI0 with LCD
1111–
16-bit EPPI1, 8-bit EPPI2
11111
Host DMA port
1111–
NAND flash controller
11111
ATAPI
111–1
High speed USB OTG
111–1
Keypad interface
111–1
MXVR
1––––
CAN ports
22–21
TWI ports
22221
SPI ports
33322
UART ports
44433
SPORTs
44433
Up/down counter
11111
Timers
11 11 11 11 8
General-purpose I/O pins
152 152 152 152 152
Memory L1 Instruction SRAM/cache 16 16 16 16 16
Configura- _{L1 Instruction SRAM}
tions
(K Bytes)
L1 Data SRAM/cache
L1 Data SRAM
48 48 48 48 48
32 32 32 32 32
32 32 32 32 32
L1 Scratchpad SRAM
44444
L1 ROM²
64 64 64 64 64
L2
128 128 128 64 –
L3 Boot ROM²
44444
Maximum core instruction rate (MHz) 533 533 600 533 600
1 _{Lockbox is a registered trademark of Analog Devices, Inc.}
2 _{This ROM is not customer-configurable.}
Specific peripherals for ADSP-BF54x Blackfin processors are
shown in Table 2.
Table 2. Specific Peripherals for ADSP-BF54x Processors
Module
EBIU (async)
NAND flash controller
ATAPI
Host DMA port (HOSTDP)
SD/SDIO controller
EPPI0
EPPI1
EPPI2
SPORT0
SPORT1
SPORT2
SPORT3
SPI0
SPI1
SPI2
UART0
UART1
UART2
UART3
High speed USB OTG
CAN0
CAN1
TWI0
TWI1
Timer 0–7
Timer 8–10
Up/down counter
Keypad interface
MXVR
GPIOs
PPPPP
PPPPP
PPP–P
PPPP–
PPP–P
PPPP–
PPPPP
PPPPP
PPP––
PPPPP
PPPPP
PPPPP
PPPPP
PPPPP
PPP––
PPPPP
PPPPP
PPP––
PPPPP
PPP–P
PP–PP
PP–P–
PPPPP
PPPP–
PPPPP
PPPP–
PPPPP
PPP–P
P––––
PPPPP
Rev. E | Page 3 of 102 | March 2014