ADSP-BF542_15 Datasheet, PDF (52/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Table 35. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter
Timing Requirement
t_WBR
BR Pulsewidth
Switching Characteristics
t_SD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
t_SE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
t_DBG
CLKOUT Low to BG Asserted Output Delay
t_EBG
CLKOUT Low to BG Deasserted Output Hold
t_DBH
CLKOUT Low to BGH Asserted Output Delay
t_EBH
CLKOUT Low to BGH Deasserted Output Hold
Min
2 × t_SCLK
Max
5.0
5.0
4.0
4.0
3.6
3.6
Unit
ns
ns
ns
ns
ns
ns
ns
CLKOUT
BR
AMSx
ADDR 19-1
ABE1-0
AWE
ARE
BG
BGH
t_WBR
tSD
tSD
tSD
t_DBG
tDBH
tSE
tSE
tSE
t_EBG
tEBH
Figure 22. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Rev. E | Page 52 of 102 | March 2014