UG-572 Datasheet, PDF (6/20 Pages) Winchester Electronics Corporation – C JACK

UG-572
Phase Voltage Sense Inputs (V1PIN_A, V1PIN_B,
V1PIN_C, and V1PIN_N Test Pins)
The phase-to-neutral voltage input connections on the
evaluation board can be directly connected to the line voltage
sources between V1PIN_A and GND_A for Phase A to neutral
voltage, between V1PIN_B and GND_B for Phase B to neutral
voltage, and between V1PIN_C and GND_C for Phase C to
neutral voltage. These voltages are attenuated using a simple
resistor divider network before they are supplied to the
ADE7933. The attenuation network on the voltage channels
is designed so that the corner frequency (3 dB frequency) of
the network matches that of the antialiasing filters in the
current channel inputs. This prevents the occurrence of large
energy errors at low power factors.
The V1PIN path in Figure 6 shows a typical connection of the
Phase A voltage inputs; the resistor divider consists in three
330 kΩ resistors (R1_A, R5_A, and R10_A) and one 1 kΩ
resistor (R14_A). The antialiasing filter R14_A/C11_A matches
the R12_A/C9_A filter in the VM path. The absolute maximum
voltages on the V1P and VM pins of the ADE7933 are ±2 V.
The D1_A, D7_A, D4_A, and D9_A diodes protect the V1P
and VM pins against voltages greater than ±2 V. The maximum
signal level permissible at the V1P pin of the ADE7933 is ±0.5 V
peak. The signal range should not exceed ±0.5 V with respect to
AGND_ADC for specified operation.
The E4_A and E5_A ferrite beads filter the high frequency
noise that may be induced into the wires.
Auxiliary Voltage Sense Inputs (V2PIN_A, V2PIN_B,
V2PIN_C, and V2PIN_N Test Pins)
The auxiliary voltage input connections on the ADE7978/
ADE7933 evaluation board can be directly connected to the line
voltage sources between V2PIN_A and GND_A for Phase A
auxiliary voltage, between V2PIN_B and GND_B for Phase B
auxiliary voltage, between V2PIN_C and GND_C for Phase C
auxiliary voltage, and between V2PIN_N and GND_N for
Phase N auxiliary voltage.
The V2PIN path in Figure 6 shows a typical connection of the
Phase A auxiliary voltage input. It is very similar to the V1PIN
path explained in the Phase Voltage Sense Inputs (V1PIN_A,
V1PIN_B, V1PIN_C, and V1PIN_N Test Pins) section.
EVAL-ADE7978EBZ User Guide
V1PIN
E4_A _{R1_A R5_A R10_A}
330kΩ 330kΩ 330kΩ
R14_A
1kΩ
C11_A
33nF
R7_A
0Ω
GND_A
R12_A
1kΩ
C9_A
33nF
GND_A
E5_A _{R2_A R6_A R11_A}
330kΩ 330kΩ 330kΩ
V2PIN
R13_A
1kΩ
C10_A
33nF
ADE7933
V1P
R17_A
0Ω
D1_A D4_A
D7_A D9_A
VM
R18_A
0Ω
D2_A D5_A
D8_A D10_A
V2P
R9_A
0Ω
Figure 6. Phase A Voltage Input Structure on the Evaluation Board
Isolated Ground Pins Management
The ADE7933 package has two isolated ground GNDISO pins:
Pin 2 and Pin 10. Figure 7 shows their management in the case
of a Phase ADE7933. For Figure 7, just add an “_A”, “_B”, “_C”,
or “_N” for Phase A, B, C, and N, respectively (for example,
Phase A C3 is “C3_A”). Internally, Pin 2 is connected to Pin 10.
The decoupling capacitors, C3 and C4 on the VDDISO pin, are
connected to the closest isolated ground pin, Pin 2. The
decoupling capacitors, C5 and C6 on the analog LDO pin and
C13 and C14 on the voltage reference pins, must be separate
from the VDDISO circuitry and are connected to the isolate
ground (Pin 10).
VDD_ISO ^ADE7933
1
C3 C4
2
GND_ISO
C5 C6
LDO
8
REF
9
GROUND CONNECTION
BETWEEN PIN 2 AND PIN 10
INTERNAL TO ADE7933
E2
GND
AGND_ADC
C13 C14
10
GND_ISO
Figure 7. Isolated Ground Pins Management
The P1 meter input constitutes the AGND_ADC1 signal (see
also Figure 5). AGND_ADC1 is then connected to the GNDISO
pin (AGND_ADC signal) through a ferrite bead, E2.
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