UG-572 Datasheet, PDF (5/20 Pages) Winchester Electronics Corporation – C JACK

EVAL-ADE7978EBZ User Guide
POWERING UP THE EVALUATION KIT BOARDS
The interface board receives power via the USB cable that is
connected to the PC. A 3.3 V regulator then powers the SDP
board microcontroller and the ADE7978/ADE7933 chipsets
populating the evaluation board. No additional power source
is required for the ADE7978/ADE7933 evaluation kit boards.
ANALOG INPUTS
Current and voltage signals are connected at the test pins placed
on the evaluation board. All analog input signals are filtered
using the on-board antialiasing filters before the signals are
connected to the ADE7933 isolated ADCs. The components
used on the board are the recommended values to be used with the
ADE7978/ADE7933.
Current Sense Inputs (IMIN_A and IPIN_A, IMIN_B and
IPIN_B, IMIN_C and IPIN_C, and IMIN_N and IPIN_N Test
Pins)
Every ADE7933 measures the voltage across a shunt at its IP
and IM pins. Figure 4 shows the structure used for the Phase A
current.
The R4_A and R8_A (similarly, R4_B, R8_B for Phase B, _C for
Phase C, and _N for Phase N) are 0 Ω resistors that do not need
to be implemented on a real meter board. The R15_A/C15_A
and R16_A/C16_A RC networks are the antialiasing filters. The
default corner frequency of these low-pass filters is 4.8 kHz
(1 kΩ/33 nF). These filters can easily be adjusted by replacing
the components on the evaluation board.
The E1, E2, and E3 ferrite beads filter the high frequency noise
that may be induced into the wires.
The absolute maximum voltage on the IP and IM pins of the
ADE7933 is ±2 V. The D3_A and D6_A diodes protect the
IP and IM pins against voltages greater than ±1 V. The
maximum signal level permissible at the IP and IM pins of
the ADE7933 is ±0.03125 V peak. The signal range should not
exceed ±0.03125 V, with respect to AGND_ADC, for specified
operation.
The Phase A shunt is connected between IPIN_A and IMIN_A
test pins.
All the other current channels (that is, Phase B and Phase C)
have an identical input structure. The Phase B shunt is
connected between the IPIN_B and IMIN_B test pins, the
Phase C shunt is connected between IPIN_C and IMIN_C, and
the Phase N shunt is connected between IPIN_N and IMIN_N.
UG-572
The shunt maximum value is function of the maximum current
to be measured on every phase:
R = ^{31.25 ×10−3} × ¹
2
I _FS
where:
31.25 ×10^−3
2
is the rms value of the full-scale voltage accepted at input.
IFS is the maximum current to be measured at the analog-to-
digital converter (ADC) IP and IM inputs. It is called the full-
scale current.
Figure 5 shows how a shunt is connected to the Phase A current
input structure. The shunt is connected between P1 and P1’
energy meter Phase A line inputs. IMIN_A and IPIN_A test
pins are connected to the shunt measurement poles, while
GND_A, the test pin that is the ground of the Phase A
ADE7933 isolated side, is connected to the ground pole of
the shunt.
E1_A
R15_A
R4_A
ADE7933
1kΩ
0kΩ
IP
IPIN
150Ω
C15_A
.033µF
E2_A
GND_A
150Ω
AGND_ADC
D3_A D6_A
IMIN
E3_A
C16_A
R16_A ^.033µF
R8_A
1kΩ
0kΩ
IM
150Ω
Figure 4. Phase A Current Input Structure on the Evaluation Board
TO P1'
METER
INPUT
IPIN
E1_A
R15_A
1kΩ
C15_A
.033µF
R4_A
0kΩ
ADE7933
IP
E2_A
TO P1
METER
INPUT
GND
D3_A D6_A
AGND_ADC
C16_A
E3_A
R16_A
.033µF _{R8_A}
1kΩ
0kΩ
IM
IMIN
Figure 5. Example of a Shunt Connection
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