SSM2604 Datasheet, PDF (6/28 Pages) Analog Devices – Low Power Audio Codec

SSM2604
Table 5. Digital Audio Interface Master Mode Timing
Limit
Parameter
tMIN
tMAX
Unit
tDST
30
ns
tDHT
10
ns
tDL
10
ns
tDDA
10
ns
tBCLKR
10
ns
tBCLKF
10
ns
tBCLKDS
45:55:00
55:45:00
Description
PBDAT setup time to BCLK rising edge
PBDAT hold time to BCLK rising edge
RECLRC/PBLRC propagation delay from BCLK falling edge
RECDAT propagation delay from BCLK falling edge
BCLK rising time (10 pF load)
BCLK falling time (10 pF load)
BCLK duty cycle (normal and USB mode)
BCLK
PBLRC/
RECLRC
t_DL
t_DST t_DHT
PBDAT
RECDAT
t_DDA
Figure 4. Digital Audio Interface Master Mode Timing
Table 6. System Clock Timing
Limit
Parameter
tMIN
tMAX
tXTIY
tMCLKDS
tXTIH
72
40:60
32
60:40:00
tXTIL
32
tCOP
20
tCOPDIV2
20
Unit Description
ns
MCLK/XTI system clock cycle time
MCLK/XTI duty cycle
ns
MCLK/XTI system clock pulse width high
ns
MCLK/XTI system clock pulse width low
ns
CLKOUT propagation delay from MCLK/XTI falling edge
ns
CLKODIV2 propagation delay from MCLK/XTI falling edge
MCLK/XTI
CLKOUT
CLKODIV2
t_XTIH
t_XTIY
t_XTIL
t_COP
t_COPDIV2
Figure 5. System (MCLK) Clock Timing
Rev. 0 | Page 6 of 28