SSM2604 Datasheet, PDF (22/28 Pages) Analog Devices – Low Power Audio Codec

SSM2604
DIGITAL AUDIO I/F, ADDRESS 0x07
Table 22. Digital Audio I/F Register Bit Map
D8
D7
D6
D5
D4
0
BCLKINV
MS
LRSWAP
LRP
D3
D2
WL [1:0]
D1
D0
FORMAT [1:0]
Table 23. Descriptions of Digital Audio I/F Register Bits
Bit Name
Description
BCLKINV
BCLK inversion control
MS
Master mode enable
LRSWAP
Swap DAC data control
LRP
WL [1:0]
Polarity control for clocks in right-justified,
left-justified, and I²S modes
Data-word length control
FORMAT [1:0]
Digital audio input format control
Settings
0 = BCLK not inverted (default)
1 = BCLK inverted
0 = enable slave mode (default)
1 = enable master mode
0 = output left- and right-channel data as normal (default)
1 = swap left- and right-channel DAC data in audio interface
0 = normal PBLRC and RECLRC (default), or DSP Submode 1
1 = invert PBLRC and RECLRC polarity, or DSP Submode 2
00 = 16 bits
01 = 20 bits
10 = 24 bits (default)
11 = 32 bits
00 = right justified
01 = left justified
10 = I²S mode (default)
11 = DSP mode
SAMPLING RATE, ADDRESS 0x08
Table 24. Sampling Rate Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
CLKODIV2 CLKDIV2
SR [3:0]
BOSR
USB
Table 25. Descriptions of Sampling Rate Register Bits
Bit Name
Description
CLKODIV2
CLKOUT divider select
CLKDIV2
Core clock divide select
SR [3:0]
BOSR
Clock setting condition
Base oversampling rate
USB
USB mode select
Settings
0 = CLKOUT is core clock (default)
1 = CLKOUT is core clock divided by 2
0 = core clock is MCLK (default)
1= core clock is MCLK divided by 2
See Table 26 and Table 27
USB mode:
0 = support for 250 fS based clock (default)
1 = support for 272 fS based clock
Normal mode:
0 = support for 256 fS based clock (default)
1 = support for 384 fS based clock
0 = normal mode enable (default)
1 = USB mode enable
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