EVAL-AD5933EB Datasheet, PDF (6/40 Pages) Analog Devices – 1 MSPS, 12-Bit Impedance Converter, Network Analyzer

AD5933
Data Sheet
I²C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.¹
Table 2.
Parameter²
fSCL
t1
t2
t3
t4
t5
t63
t7
t8
t9
t10
t11
Cb
Limit at TMIN, TMAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
250
20 + 0.1 Cb4
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT, data hold time
tHD, DAT, data hold time
tSU, STA, setup time for repeated start
tSU, STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tF, rise time of SDA when transmitting
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1 _{See Figure 2.}
2 _{Guaranteed by design and characterization, not production tested.}
3 _{A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) to bridge the undefined falling edge of SCL.}
4 _{Cb is the total capacitance of one bus line in picofarads. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.}
SDA
t₉
t₃
t₁₀ t₁₁
t₄
SCL
t₄
START
CONDITION
t₆
t₂
t₅
t₇
t₁
REPEATED
START
CONDITION
Figure 2. I²C Interface Timing Diagram
t₈
STOP
CONDITION
Rev. E | Page 6 of 40