EVAL-AD5933EB Datasheet, PDF (13/40 Pages) Analog Devices – 1 MSPS, 12-Bit Impedance Converter, Network Analyzer

Data Sheet
AD5933
SYSTEM DESCRIPTION
MCLK
OSCILLATOR
MICROCONTROLLER
SCL
SDA
I²C
INTERFACE
REAL IMAGINARY
REGISTER REGISTER
DDS
CORE
(27 BITS)
COS SIN
DAC
TEMPERATURE
SENSOR
AD5933
R_OUT
VOUT
Z(ω)
MAC CORE
(1024 DFT)
WINDOWING
OF DATA
MCLK
ADC
(12 BITS)
PROGRAMMABLE
GAIN AMPLIFIER
×5
LPF
×1
RFB
VIN
VDD/2
Figure 17. Block Overview
The AD5933 is a high precision impedance converter system
solution that combines an on-board frequency generator with a
12-bit, 1 MSPS ADC. The frequency generator allows an external
complex impedance to be excited with a known frequency. The
response signal from the impedance is sampled by the on-board
ADC and DFT processed by an on-board DSP engine. The DFT
algorithm returns both a real (R) and imaginary (I) data-word at
each frequency point along the sweep. The impedance magnitude
and phase are easily calculated using the following equations:
Magnitude = R² + I ²
Phase = tan^−1(I/R)
To characterize an impedance profile Z(ω), generally a frequency
sweep is required, like that shown in Figure 18.
The AD5933 permits the user to perform a frequency sweep with
a user-defined start frequency, frequency resolution, and number
of points in the sweep. In addition, the device allows the user to
program the peak-to-peak value of the output sinusoidal signal as
an excitation to the external unknown impedance connected
between the VOUT and VIN pins.
Table 5 gives the four possible output peak-to-peak voltages and
the corresponding dc bias levels for each range for 3.3 V. These
values are ratiometric with VDD. So for a 5 V supply
Output Excitation Voltage for Range 1 = 1.98 × ^5.0 = 3 V p − p
3.3
Output DC Bias Voltage for Range 1 = 1.48 × ^5.0 = 2.24 V p − p
3.3
Table 5. Voltage Levels Respective Bias Levels for 3.3 V
Range
Output Excitation
Voltage Amplitude
Output DC Bias Level
1
1.98 V p-p
1.48 V
2
0.97 V p-p
0.76 V
3
383 mV p-p
0.31 V
4
198 mV p-p
0.173 V
FREQUENCY
Figure 18. Impedance vs. Frequency Profile
The excitation signal for the transmit stage is provided on-chip
using DDS techniques that permit subhertz resolution. The receive
stage receives the input signal current from the unknown impedance,
performs signal processing, and digitizes the result. The clock for
the DDS is generated from either an external reference clock,
which is provided by the user at MCLK, or by the internal
oscillator. The clock for the DDS is determined by the status of
Bit D3 in the control register (see Register Address 0x81 in the
Register Map section).
Rev. E | Page 13 of 40