EVAL-AD5933EB Datasheet, PDF (18/40 Pages) Analog Devices – 1 MSPS, 12-Bit Impedance Converter, Network Analyzer

AD5933
TWO-POINT CALIBRATION
Alternatively, it is possible to minimize this error by assuming
that the frequency variation is linear and adjusting the gain
factor with a two-point calibration. Figure 23 shows an
impedance profile based on a two-point gain factor calculation.
101.5
101.0
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz
T_A = 25°C
MEASURED CALIBRATION IMPEDANCE = 100kΩ
100.5
100.0
99.5
99.0
98.5
54
56
58
60
62
64
66
FREQUENCY (kHz)
Figure 23. Impedance Profile Using a Two-Point Gain Factor Calculation
TWO-POINT GAIN FACTOR CALCULATION
This is an example of a two-point gain factor calculation
assuming the following:
Output excitation voltage = 2 V (p-p)
Calibration impedance value, ZUNKNOWN = 100.0 kΩ
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 100 kΩ
Calibration frequencies = 55 kHz and 65 kHz
Typical values of the gain factor calculated at the two calibration
frequencies read
Gain factor calculated at 55 kHz is 1.031224E-09
Gain factor calculated at 65 kHz is 1.035682E-09
Difference in gain factor (∆GF) is 1.035682E-09 −
1.031224E-09 = 4.458000E-12
Frequency span of sweep (∆F) = 10 kHz
Therefore, the gain factor required at 60 kHz is given by
 ^{4.458000E -12}
 _{10 kHz}
×
5
kHz


+
1.031224
×
10
-9
The required gain factor is 1.033453E-9.
The impedance is calculated as previously described.
Data Sheet
GAIN FACTOR SETUP CONFIGURATION
When calculating the gain factor, it is important that the receive
stage operate in its linear region. This requires careful selection
of the excitation signal range, current-to-voltage gain resistor,
and PGA gain.
CURRENT-TO-VOLTAGE
GAIN SETTING RESISTOR
RFB
VOUT
Z_UNKNOWN
VIN
VDD/2
LPF
PGA
(×1 OR ×5)
ADC
Figure 24. System Voltage Gain
The gain through the system shown in Figure 24 is given by
Ouput ExcitationVoltage Range ×
Gain Setting Re sistor _{× PGA Gain}
Z_UNKNOWN
For this example, assume the following system settings:
VDD = 3.3 V
Gain setting resistor = 200 kΩ
ZUNKNOWN = 200 kΩ
PGA setting = ×1
The peak-to-peak voltage presented to the ADC input is
2 V p-p. However, if a PGA gain of ×5 was chose, the voltage
would saturate the ADC.
GAIN FACTOR RECALCULATION
The gain factor must be recalculated for a change in any of the
following parameters:
• Current-to-voltage gain setting resistor
• Output excitation voltage
• PGA gain
Rev. E | Page 18 of 40