5962-88766013A Datasheet, PDF (6/16 Pages) Analog Devices – LC2MOS 12-Bit DACPORTs

AD7245A/AD7248A
AD7248A PIN FUNCTION DESCRIPTIONS
(ANY PACKAGE)
Pin Mnemonic Description
l V_SS
Negative Supply Voltage (0 V for single
supply operation).
2 R_OFS
Bipolar Offset Resistor. This provides
access to the on-chip application resistors
and allows different output voltage ranges.
3 REF OUT Reference Output. The on-chip reference
is provided at this pin and is used when
configuring the part for bipolar outputs.
4 AGND
Analog Ground.
5 DB7
Data Bit 7.
6 DB6
Data Bit 6.
7 DB5
Data Bit 5.
8 DB4
Data Bit 4.
9 DB3
Data Bit 3.
10 DGND
Digital Ground.
11 DB2
Data Bit 2/Data Bit 10.
12 DB1
Data Bit 1/Data Bit 9.
13 DB0
Data Bit 0 (LSB)/Data Bit 8.
Pin Mnemonic Description
14 CSMSB
15 CSLSB
16 WR
17 LDAC
Chip Select Input for MS Nibble. (Active
LOW). This selects the upper 4 bits of the
input latch. Input data is right justified.
Chip Select Input for LS byte. (Active
LOW). This selects the lower 8 bits of the
input latch.
Write Input. This is used in conjunction
with CSMSB and CSLSB to load data
into the input latch of the AD7248A.
Load DAC Input (Active LOW). This is
an asynchronous input which when active
transfers data from the input latch to the
DAC latch.
18 V_DD
19 R_FB
Positive Supply Voltage.
Feedback Resistor. This allows access to
the amplifier’s feedback loop.
20 V_OUT
Output Voltage. Three different output
voltage ranges can be chosen: 0 V to 5 V,
0 V to 10 V or –5 V to +5 V.
DIP and SOIC
V_SS 1
20 VOUT
R_OFS 2
19 R_FB
REF OUT 3
18 V_DD
AGND 4
17 LDAC
(MSB) DB7 5
AD7248A
TOP VIEW
16 WR
DB6 6 ^{(NOT TO SCALE)} 15 CSLSB
DB5 7
14 CSMSB
DB4 8
13 DB0 (LSB)
DB3 9
12 DB1
DGND 10
11 DB2
AD7248A PIN CONFIGURATIONS
PLCC
AGND 4
(MSB) DB7 5
DB6 6
DB5 7
DB4 8
3 2 1 20 19
PIN 1
IDENTIFIER
AD7248A
TOP VIEW
(NOT TO SCALE)
18 V_DD
17 LDAC
16 WR
15 CSLSB
14 _CSMSB
9 10 11 12 13
LCCC
3 2 1 20 19
AGND 4
(MSB) DB7 5
DB6 6
DB5 7
DB4 8
AD7248A
TOP VIEW
(NOT TO SCALE)
18 V_DD
17 _LDAC
16 WR
15 CSLSB
14 CSMSB
9 10 11 12 13
–6–
REV. B