5962-88766013A Datasheet, PDF (13/16 Pages) Analog Devices – LC2MOS 12-Bit DACPORTs

AD7245A/AD7248A
Table V. Sample Program for Loading AD7245A from 8086
ASSUME DS: DACLOAD, CS: DACLOAD
DACLOAD SEGMENT AT 000
00 8CC9
MOV CS, : DEFINE DATA SEGMENT
CS
REGISTER
02 8ED9
MOV DS, : EQUAL TO CODE
CX
SEGMENT REGISTER
04 BF00D0 0MOV DI, : LOAD DI WITH D000
#D000
07 C705 MOV MEM, : DAC LOADED WITH WXYZ
“YZWX” #YZWX
0B EA00 00
0E 00 FF
: CONTROL IS RETURNED TO
THE MONITOR PROGRAM
In a multiple DAC system the double buffering of the AD7245A
allows the user to simultaneously update all DACs. In Figure
13, a 12-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropri-
ate address, CS4 (i.e., LDAC) is brought LOW, updating all the
DACs simultaneously.
8086
ALE
WR
AD15
AD0
ADDRESS BUS
16-BIT
LATCH
ADDRESS ^CS1
DECODE
CS4
DATA BUS
CS AD7245A*
LDAC
WR
DB11
DB0
MC68000
AS
DTACK
R/W
ADDRESS BUS
ADDRESS
DECODE
CS
LDAC
AD7245A*
WR
DB11
DB0
D0–D15
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 14. AD7245A to MC68000 Interface
Table VI. Sample Routine for Loading AD7245A from 68000
01000 MOVE.W
MOVE.W
MOVE.B
TRAP
#X,D0
D0,$E000
#228,D7
#14
The desired DAC data,
X, is loaded into Data
Register 0. X may be any
value between 0 and 4094
(decimal) or 0 and OFFF
(hexadecimal).
The Data X is transferred
between D0 and the
DAC Latch.
Control is returned to
the System Monitor
Program using these two
instructions.
CS AD7245A*
LDAC
WR
DB11
DB0
CS AD7245A*
LDAC
WR
DB11
DB0
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 13. AD7245A to 8086 Multiple DAC Interface
AD7245A—MC68000 INTERFACE
Interfacing between the MC68000 and the AD7245A is accom-
plished using the circuit of Figure 14. Once again the AD7245A
is used in the single buffered mode. A software routine for load-
ing data to the AD7245A is given in Table VI. In this example
the AD7245A is located at address E000, and the 12-bit word is
written to the DAC in one MOVE instruction.
MICROPROCESSOR INTERFACE—AD7248A
Figure 15 shows the connection diagram for interfacing the
AD7248A to both the 8085A and 8088 microprocessors. This
scheme is also suited to the Z80 microprocessor, but the Z80
address/data bus does not have to be demultiplexed. Data to be
loaded to the AD7248A is right justified. The AD7248A is
memory mapped with a separate memory address for the input
latch high byte, the input latch low byte and the DAC latch.
Data is first written to the AD7248A input latch in two write
operations. Either the high byte or the low byte data can be
written first to the AD7248A input latch. A write to the AD7248A
DAC latch address transfers the input latch data to the DAC
latch and updates the output voltage. Alternatively, the LDAC
input can be asynchronous or can be common to a number
of AD7248As for simultaneous updating of a number of volt-
age channels.
A8–A15
ALE
8085A/8088
WR
ADDRESS BUS
OCTAL
LATCH
ADDRESS
DECODE
CSLSB
CSMSB
LDAC
WR ^AD7248A*
DB0–DB7
REV. B
–13–
AD0–AD7
ADDRESS/DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
Figure 15. AD7248A to 8085A/8088 Interface