5962-88766013A Datasheet, PDF (2/16 Pages) Analog Devices – LC2MOS 12-Bit DACPORTs

AD7245A/AD7248A–SPECIFICATIONS (V_DD = +12 V to +15 V,¹V_SS = O V or –12 V to –15 V,¹
AGND = DGND = O V, R_L = 2 k⍀, C_L = 100 pF. All specifications T_MIN to T_MAX unless otherwise noted.)
Parameter
A²
B²
T²
Version Version Version Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
Relative Accuracy @ 25°C³
T_MIN to T_MAX
T_MIN to T_MAX
Differential Nonlinearity³
Unipolar Offset Error @ 25°C³
T_MIN to T_MAX
Bipolar Zero Error @ 25°C³
T_MIN to T_MAX
DAC Gain Error^{3, 6}
Full-Scale Output Voltage Error⁷ @ 25°C
∆Full Scale/∆V_DD
∆Full Scale/∆V_SS
Full-Scale Temperature Coefficient⁸
REFERENCE OUTPUT
REF OUT @ 25°C
∆REF OUT/∆V_DD
Reference Temperature Coefficient
Reference Load Change
(∆REF OUT vs. ∆I)
12
± 3/4
±1
±1
±3
±5
±3
±5
±2
± 0.2
± 0.06
± 0.01
± 40
12
± 1/2
± 3/4
± 1/2
±1
±3
±5
±2
±4
±2
± 0.2
± 0.06
± 0.01
± 30
4.99/5.01 4.99/5.01
2
2
± 25
± 25
–1
–1
12
± 1/2
± 3/4
±1
±3
±5
±2
±4
±2
± 0.2
± 0.06
± 0.01
± 40
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
% of FSR max
% of FSR/V max
% of FSR/V max
ppm of FSR/°C max
V_DD = 15 V ± 10%
Guaranteed Monotonic
V_SS = 0 V or –12 V to –15 V⁴
Typical Tempco is ± 3 ppm of FSR⁵/°C.
R_OFS connected to REF OUT; V_SS = –12 V to –15 V⁴
Typical Tempco is ± 3 ppm of FSR⁵/°C.
V_DD = 15 V
V_DD = +12 V to +15 V⁴
V_SS = –12 V to –15 V⁴
V_DD = 15 V
4.99/5.01 V min/V max
2
mV/V max
± 35
ppm/°C typ
–1
mV max
V_DD = 15 V
V_DD = 12 V to 15 V⁴
Reference Load Current Change (0–100 µA)
DIGITAL INPUTS
Input High Voltage, V_INH
Input Low Voltage, V_INL
Input Current, I_IN
Input Capacitance⁹
2.4
2.4
0.8
0.8
± 10
± 10
8
8
2.4
V min
0.8
V max
± 10
µA max
8
pF max
V_IN = 0 V to V_DD
ANALOG OUTPUTS
Output Range Resistors
Output Voltage Ranges¹⁰
DC Output Impedance
AC CHARACTERISTICS⁹
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Output Voltage Slew Rate
Digital Feedthrough³
Digital-to-Analog Glitch Impulse
15/30
5, 10
5, 10,
±5
0.5
15/30
5, 10
5, 10,
±5
0.5
7
7
7
7
2
2
10
10
30
30
15/30
5, 10
5, 10,
±5
0.5
kΩ min/kΩ max
V
V
Ω typ
10
µs max
10
µs max
1.5
V/µs min
10
nV-s typ
30
nV-s typ
V_SS = 0 V; Pin Strappable
V_SS = –12 V to –15 V;⁴ Pin Strappable
Settling Time to Within ± 1/2 LSB of Final Value
DAC Latch All 0s to All 1s
DAC Latch All 1s to All 0s; V_SS = –12 V to –15 V⁴
POWER REQUIREMENTS
V_DD
V_SS
I_DD @ 25°C
T_MlN to T_MAX
I_SS (Dual Supplies)
+10.8/
+16.5
–10.8/
–16.5
9
10
3
+10.8/
+16.5
–10.8/
–16.5
9
10
3
+10.8/
+16.5
–10.8/
–16.5
9
12
5
V min/
V max
V min/
V max
mA max
mA max
mA max
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Output Unloaded; Typically 5 mA
Output Unloaded
Output Unloaded; Typically 2 mA
NOTES
1_{Power supply tolerance is ± 10%.}
2_{Temperature ranges are as follows: A/B Versions; –40°C to +85°C; T Version; –55°C to +125°C.}
3_{See Terminology.}
4_{With appropriate power supply tolerances.}
5_{FSR means Full-Scale Range and is 5 V for the 0 V to 5 V output range and 10 V for both the 0 V to 10 V and ± 5 V output ranges.}
6_{This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.}
7_{This error is calculated with respect to an ideal 4.9988 V on the 0 V to 5 V and ± 5 V ranges; it is calculated with respect to an ideal 9.9976 V on the 0 V to 10 V}
range. It includes the effects of internal voltage reference, gain and offset errors.
8_{Full-Scale TC = ∆FS/∆T, where ∆FS is the full-scale change from TA = 25°C to TMIN or TMAX.}
9_{Guaranteed by design and characterization, not production tested.}
10_{0 V to 10 V output range is available only when VDD ≥ +14.25 V.}
Specifications subject to change without notice.
–2–
REV. B