5962-88766013A Datasheet, PDF (11/16 Pages) Analog Devices – LC2MOS 12-Bit DACPORTs

AD7245A/AD7248A
UNIPOLAR (0 V TO 5 V) CONFIGURATION
The 0 V to 5 V output voltage range is achieved by tying R_OFS,
R_FB and V_OUT together. For this output range the AD7245A/
AD7248A can be operated single supply (V_SS = 0 V) or dual sup-
ply. The table for output voltage versus digital code is as in Table
III, with 2 × V_REF replaced by V_REF. Note that for this range
1
LSB
=
V_REF(2^–12)
=
V_REF
؋
 ₁
 4096 
.
BIPOLAR CONFIGURATION
The bipolar configuration for the AD7245A/AD7248A, which
gives an output voltage range from –5 V to +5 V, is achieved by
connecting the R_OFS input to REF OUT and connecting R_FB
and V_OUT. The AD7245A/AD7248A must be operated from
dual supplies to achieve this output voltage range. The code
table for bipolar operation is shown in Table IV.
Table IV. Bipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output, V_OUT
1111 1111
 ₂₀₄₇ 
1 1 1 1 +V_REF × _{ 2048 }
1000 0000
1000 0000
0111 1111
0001
0000
1111
 ₁
+V_REF × _{ 2048 }
0V
 ₁
–V_REF × _{ 2048 }
0000 0000
 ₂₀₄₇ 
0 0 0 1 –V_REF × _{ 2048 }
0000 0000
0000
–V_REF ×
 ₂₀₄₈ 
 2048 
=
– V_REF
 ₁
NOTE: 1 LSB = 2 × V_REF(2^–11) = V_{REF  2048 }
AGND BIAS
The AD7245A/AD7248A AGND pin can be biased above sys-
tem GND (AD7245A/AD7248A DGND) to provide an offset
“zero” analog output voltage level. With unity gain on the
amplifier (R_OFS = V_OUT = R_FB) the output voltage, V_OUT is
expressed as:
V_OUT = V_BIAS + D ؋ V_REF
where D is a fractional representation of the digital word in the
DAC latch and V_BIAS is the voltage applied to the AD7245A/
AD7248A AGND pin.
Because the current flowing out of the AGND pin varies with
digital code, the AGND pin should be driven from a low imped-
ance source. A circuit configuration is outlined for AGND bias
in Figure 9 using the AD589, a +1.23 V bandgap reference.
If a gain of 2 is used on the buffer amplifier the output voltage,
V_OUT is expressed as
V_OUT = 2(V_BIAS + D ؋ V_REF)
In this case care must be taken to ensure that the maximum
output voltage is not greater than V_DD –3 V. The V_DD–V_OUT
overhead must be greater than 3 V to ensure correct operation
of the part. Note that V_DD and V_SS for the AD7245A/AD7248A
must be referenced to DGND (system GND). The entire circuit
can be operated in single supply with the V_SS pin of the
AD7245A/AD7248A connected to system GND.
0.1␮F
10⍀
+
10␮F
15V
27k⍀
REF OUT
R_OFS
V_DD
2R
2R
R_FB
V_BIAS
AGND
+
– ^AD589
REF
V_REF
DAC
V_OUT
AD7245A/AD7248A*
DGND
V_SS
*DIGITAL CIRCUITRY
OMITTED FOR CLARITY.
Figure 9. AGND Bias Circuit
SYSTEM
GND
PROGRAMMABLE CURRENT SINK
Figure 10 shows how the AD7245A/AD7248A can be config-
ured with a power MOSFET transistor, the VN0300M, to
provide a programmable current sink from V_DD or V_SOURCE.
The VN0300M is placed in the feedback of the AD7245A/
AD7248A amplifier. The entire circuit can be operated in single
supply by tying the V_SS of the AD7245A/AD7248A to AGND.
The sink current, I_SINK, can be expressed as:
I_SINK =
D × V_REF
R1
0.1␮F
10⍀
+
10␮F
V_SOURCE
REF OUT
R_OFS
V_DD
LOAD
2R
2R
R_FB
REF
V_REF
DAC
V_OUT
AD7245A/AD7248A*
DGND AGND
V_SS
*DIGITAL CIRCUITRY
OMITTED FOR CLARITY.
I_SINK
VN0300M
R1
Figure 10. Programmable Current Sink
Using the VN0300M, the voltage drop across the load can typi-
cally be as large as V_SOURCE –6 V) with V_OUT of the DAC at
5 V. Therefore, for a current of 50 mA flowing in the R1 (with
all 1s in the DAC register) the maximum load is 200 Ω with
V_SOURCE = 15 V. The VN0300M can actually handle currents
up to 500 mA and still function correctly in the circuit, but in
practice the circuit must be used with larger values of V_SOURCE
otherwise it requires a very small load.
REV. B
–11–