AD9957_07 Datasheet, PDF (50/60 Pages) Analog Devices – 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC

AD9957
Control Function Register 1 (CFR1)
Address 0x00, four bytes are assigned to this register.
Table 18. Bit Descriptions for CFR1 Register
Bit
No. Mnemonic
Description
31 RAM Enable
0: disables RAM playback functionality (default).
1: enables RAM playback functionality.
30:20 Not Available
28 RAM Playback
Destination
Ineffective unless Bit 31 = 1.
0: RAM playback data routed to baseband scaling multipliers (default).
1: RAM playback data routed to baseband I/Q data path.
27:26 Not Available
25:24 Operating Mode 00: quadrature modulation mode (default).
01: single tone mode.
1x: interpolating DAC mode.
23 Manual OSK
Ineffective unless Bits<9:8> = 10b.
External Control
0: OSK pin inoperative (default).
1: OSK pin enabled for manual OSK control (see the Output Shift Keying (OSK) section).
22 Inverse Sinc Filter 0: inverse sinc filter bypassed (default).
Enable
1: inverse sinc filter active.
21 Clear CCI
This bit is automatically cleared by the serial I/O port controller. This operation requires several internal clock
cycles to complete, during which time the data supplied to the CCI input by the baseband signal chain is
ignored. The inputs are forced to all zeros to flush the CCI data path, after which the CCI accumulators are reset.
0: normal operation of the CCI filter (default).
1: initiates an asynchronous reset of the accumulators in the CCI filter.
20:17 Not Available
16 Select DDS Sine Ineffective unless Bits<25:24> = 01b.
Output
0: cosine output of the DDS is selected (default).
1: sine output of the DDS is selected.
15:14 Not Available
13 Autoclear Phase 0: normal operation of the DDS phase accumulator (default).
Accumulator
1: synchronously resets the DDS phase accumulator any time I/O_UPDATE is asserted or a profile
change occurs.
12 Not Available
11 Clear Phase
Accumulator
0: normal operation of the DDS phase accumulator (default).
1: asynchronous, static reset of the DDS phase accumulator.
10 Load ARR @ I/O
Update
0: normal operation of the OSK amplitude ramp rate timer (default).
1: OSK amplitude ramp rate timer reloaded any time I/O_UPDATE is asserted or a profile change occurs.
9
OSK (Output Shift 0: OSK disabled (default).
Keying) Enable
1: OSK enabled.
8
Select Auto-OSK Ineffective unless Bit 9 = 1.
0: manual OSK enabled (default).
1: automatic OSK enabled.
7
Digital Power-
Down
This bit is effective without the need for an I/O update.
0: clock signals to the digital core are active (default).
1: clock signals to the digital core are disabled.
6
DAC Power-Down 0: DAC clock signals and bias circuits are active (default).
1: DAC clock signals and bias circuits are disabled.
5
REFCLK Input
Power-Down
This bit is effective without the need for an I/O update.
0: REFCLK input circuits and PLL are active (default).
1: REFCLK input circuits and PLL are disabled.
4
Auxiliary DAC
Power-Down
0: auxiliary DAC clock signals and bias circuits are active (default).
1: auxiliary DAC clock signals and bias circuits are disabled.
Rev. 0 | Page 50 of 60