AD9957_07 Datasheet, PDF (36/60 Pages) Analog Devices – 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC

AD9957
ADDITIONAL FEATURES
OUTPUT SHIFT KEYING (OSK)
The OSK function (Figure 53) is only available in single tone
mode. It allows the user to control the output signal amplitude
of the DDS. Both manual and automatic modes are available.
OSK
60
OSK ENABLE
AUTO OSK ENABLE
MANUAL OSK EXTERNAL
LOAD ARR AT I/O_UPDATE
AMPLITUDE RAMP RATE ¹⁶
(ASF<31:16>)
AMPLITUDE SCALE FACTOR ¹⁴
(ASF<15:2>)
AMPLITUDE STEP SIZE
2
(ASF<1:0>)
14
OSK
CONTROLLER
TO DDS
AMPLITUDE
CONTROL
PARAMETER
DDS CLOCK
Figure 53. OSK Block Diagram
The operation of the OSK function is governed by four control
register bits, the external OSK pin, and the entire 32 bits of the
ASF register. The primary control for the OSK block is the OSK
enable bit. When this bit is set, the OSK function is enabled,
otherwise, the OSK function is disabled. When disabled, the
other OSK input controls are ignored and the internal clocks are
shut down to conserve power.
When the OSK function is enabled, automatic and manual
operation is selected via the select auto-OSK bit. When this bit
is set, the automatic mode is active, otherwise, the manual
mode is active.
Manual OSK
In manual mode, output amplitude is varied by successive write
operations to the amplitude scale factor portion of the ASF
register. The rate at which amplitude changes can be applied to
the output signal is limited by the speed of the serial I/O port.
In manual mode, the OSK pin functionality depends on the
state of the manual OSK external control bit. When this bit is
clear, the OSK pin is inoperative. When this bit is set, the OSK
pin can be used to switch the output amplitude between the
programmed amplitude scale factor value and zero. A Logic 0
on the OSK pin forces the output amplitude to zero whereas a
Logic 1 on the OSK pin causes the output amplitude to be
scaled by the amplitude scale factor value.
Automatic OSK
In automatic mode, the OSK function automatically generates
a linear amplitude vs. time profile (or amplitude ramp). The
amplitude ramp is controlled via three parameters, as follows:
• The maximum amplitude scale factor
• The amplitude step size
• The time interval between steps
The amplitude ramp parameters reside in the 32-bit ASF
register and are programmed via the serial I/O port. The
amplitude step interval is set using the 16-bit amplitude ramp
rate portion of the ASF register (Bits<31:16>). The maximum
amplitude scale factor is set using the 14-bit amplitude scale
factor in the ASF register (Bits<15:2>). The amplitude step size
is set using the two-bit amplitude step size portion of the ASF
register (Bits<1:0>). The direction of the ramp (positive or
negative slope) is controlled by the external OSK pin. When the
OSK pin is a Logic 1, the slope is positive; otherwise, it is
negative.
The step interval is controlled by a 16-bit programmable timer
that is clocked at a rate of ¼ fSYSCLK. The timer period sets the
interval between amplitude steps. The step time interval (Δt)
is given by
Δt = ^4M
f_SYSCLK
where M is the 16-bit number stored in the amplitude ramp rate
portion of the ASF register. For example, if fSYSCLK = 750 MHz
and M = 23218 (0x5AB2), then Δt ≈ 123.8293 μs.
The output of the OSK function is a 14-bit unsigned data bus
that controls the amplitude of the DDS output (as long as the
OSK enable bit is Logic 1). When the OSK pin is Logic 1, the
OSK output value starts at 0 and increments by the programmed
amplitude step size until it reaches the programmed maximum
amplitude value. When the OSK pin is Logic 0, the OSK output
starts at its present value and decrements by the programmed
amplitude step size until it reaches 0.
The OSK output does not necessarily attain the maximum
amplitude—the OSK pin may switch to Logic 0 before attaining
the maximum value.
The OSK output does not necessarily reach a value of zero—the
OSK pin may switch to Logic 1 before attaining the zero value.
The OSK output is initialized to 0 at power-up. It is also set to 0
when the OSK enable bit is Logic 0 or when the OSK enable bit
is Logic 1, but the select auto-OSK bit is Logic 0.
The amplitude step size of the OSK output is set by the
amplitude step size bits in the ASF register according to the
values listed in Table 10. The step size refers to the LSB weight
of the 14-bit OSK output.
The OSK output cannot exceed the maximum amplitude value
programmed into the ASF register.
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