AD9957_07 Datasheet, PDF (35/60 Pages) Analog Devices – 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC

PLL CHARGE PUMP
The charge pump current (ICP) is programmable to provide the
user with additional flexibility to optimize the PLL performance.
Table 9 lists the bit settings vs. the nominal charge pump
current.
Table 9. PLL Charge Pump Current
ICP (CFR3<21:19>)
Charge Pump Current (ICP in μA)
000
212
001
237
010
262
011
287
100
312
101
337
110
363
111
387
EXTERNAL PLL LOOP FILTER COMPONENTS
The PLL_LOOP_FILTER pin provides a connection interface to
attach the external loop filter components. The ability to use
custom loop filter components gives the user more flexibility to
optimize the PLL performance. The PLL and external loop filter
components are shown in Figure 52.
AVDD
C1
R1
C2
PLL IN
PLL_LOOP_FILTER
2
REFCLK PLL
PFD
CP
VCO
PLL OUT
÷N
Figure 52. REFCLK PLL External Loop Filter
In the prevailing literature, this configuration yields a third-
order, Type II PLL. To calculate the loop filter component
values, begin with the feedback divider value (N), the gain of
the phase detector (KD), and the gain of the VCO (KV) based on
the programmed VCO SEL bit settings (see Table 1 for KV). The
loop filter component values depend on the desired open-loop
bandwidth (fOL) and phase margin (φ), as follows:
AD9957
R1 =
πNf_OL
K_DK_V
⎜⎜⎝⎛^{1 +}
1
sin(φ)
⎟⎟⎠⎞
(7)
C1
=
K _DK_V tan(φ)
2N (πf_OL )²
(8)
C2
=
K_DK_V
N (2πf _OL
)²
⎜⎜⎝⎛
1
− sin(φ)
cos(φ)
⎟⎟⎠⎞
(9)
where:
KD equals the programmed value of ICP.
KV is taken from Table 1.
Ensure that proper units are used for the variables in Equation 7
through Equation 9. ICP must be in amps, not μA as appears in
Table 9; KV must be in Hz/V, not MHz/V as listed in Table 1; the
loop bandwidth (fOL) must be in Hz; the phase margin (φ) must
be in radians.
For example, suppose the PLL is programmed such that
ICP = 287 μA, KV = 625 MHz/V, and N = 25. If the desired loop
bandwidth and phase margin are 50 kHz and 45°, respectively,
the loop filter component values are R1 = 52.85 Ω, C1 =
145.4 nF, and C2 = 30.11 nF.
PLL LOCK INDICATION
When the PLL is in use, the PLL_LOCK pin provides an active
high indication that the PLL has locked to the REFCLK input
signal. When the PLL is bypassed the PLL_LOCK pin defaults
to Logic 0.
Rev. 0 | Page 35 of 60