AD9957_07 Datasheet, PDF (2/60 Pages) Analog Devices – 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC

AD9957
TABLE OF CONTENTS
Features .............................................................................................. 1
RAM State Machine ................................................................... 26
Applications....................................................................................... 1
RAM Trigger (RT) Pin............................................................... 26
General Description ......................................................................... 1
Load/Retrieve RAM Operation................................................ 27
Functional Block Diagram .............................................................. 1
RAM Playback Operation ......................................................... 27
Specifications..................................................................................... 4
Overview of RAM Playback Modes......................................... 28
Electrical Specifications............................................................... 4
RAM Ramp-Up Mode........................................................... 28
Absolute Maximum Ratings............................................................ 7
RAM Bidirectional Ramp Mode .......................................... 29
ESD Caution.................................................................................. 7
RAM Continuous Bidirectional Ramp Mode .................... 31
Pin Configuration and Function Descriptions............................. 8
RAM Continuous Recirculate Mode................................... 32
Typical Performance Characteristics ........................................... 11
Clock Input (REF_CLK)................................................................ 33
Modes of Operation ....................................................................... 15
REFCLK Overview..................................................................... 33
Overview...................................................................................... 15
Crystal Driven REF_CLK ......................................................... 33
Quadrature Modulation Mode ................................................. 16
Direct Driven REF_CLK ........................................................... 33
BlackFin Interface (BFI) ............................................................ 17
Phase-Locked Loop (PLL) Multiplier...................................... 34
Interpolating DAC Mode .......................................................... 18
PLL Charge Pump ...................................................................... 35
Single Tone Mode ....................................................................... 19
External PLL Loop Filter Components ................................... 35
Signal Processing ............................................................................ 20
PLL Lock Indication .................................................................. 35
Parallel Data Clock (PDCLK)................................................... 20
Additional Features ........................................................................ 36
Transmit Enable Pin (TxEnable) .............................................. 20
Output Shift Keying (OSK)....................................................... 36
Input Data Assembler ................................................................ 21
Manual OSK............................................................................ 36
Inverse CCI Filter ....................................................................... 22
Automatic OSK....................................................................... 36
Fixed Interpolator (4×) .............................................................. 22
Profiles ......................................................................................... 37
Programmable Interpolating Filter .......................................... 23
I/O_UPDATE Pin ...................................................................... 37
Quadrature Modulator .............................................................. 23
Automatic I/O Update ............................................................... 37
DDS Core..................................................................................... 24
Power-Down Control ................................................................ 38
Inverse Sinc Filter ....................................................................... 24
General-Purpose I/O (GPIO) Port .......................................... 38
Output Scale Factor (OSF) ........................................................ 25
Synchronization of Multiple Devices........................................... 39
14-Bit DAC .................................................................................. 25
Serial Programming ....................................................................... 42
Auxiliary DAC ........................................................................ 25
Control Interface—Serial I/O ................................................... 42
RAM Control .................................................................................. 26
General Serial I/O Operation ................................................... 42
RAM Overview........................................................................... 26
Instruction Byte .......................................................................... 42
RAM Segment Registers............................................................ 26
Instruction Byte Information Bit Map ................................ 42
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