EVAL-ADF4108EBZ1 Datasheet, PDF (5/20 Pages) Analog Devices – PLL Frequency Synthesizer

Data Sheet
ADF4108
TIMING CHARACTERISTICS
AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to
TMAX, unless otherwise noted.
Table 2.
Parameter¹
t1
t2
t3
t4
t5
t6
Limit² (B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
1 _{Guaranteed by design but not production tested.}
2 _{Operating temperature range (B Version) is −40°C to +85°C.}
t₃
t₄
CLOCK
DATA ^{DB23 (MSB)}
t₁
t₂
DB22
LE
LE
DB2
DB1
DB0 (LSB)
(CONTROL BIT C1)
(CONTROL BIT C2)
t₆
t₅
Figure 2. Timing Diagram
Rev. B | Page 5 of 20