EVAL-ADF4108EBZ1 Datasheet, PDF (10/20 Pages) Analog Devices – PLL Frequency Synthesizer

ADF4108
PHASE FREQUENCY DETECTOR AND
CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 13 is a simplified schematic. The PFD includes a
programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse (see Figure 16). Use of
the minimum antibacklash pulse width is not recommended.
HI
D1 Q1 ^UP
V_P
CHARGE
PUMP
R DIVIDER
U1
CLR1
PROGRAMMABLE
DELAY
U3
CP
ABP2 ABP1
CLR2 _DOWN
HI
D2 Q2
U2
N DIVIDER
CPGND
Figure 13. PFD Simplified Schematic and Timing (in Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4108 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 18 shows the full truth table. Figure 14 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When the lock detect precision
(LDP) bit in the R counter latch is set to 0, digital lock detect is
set high when the phase error on three consecutive phase
detector (PD) cycles is less than 15 ns. With LDP set to 1, five
Data Sheet
consecutive cycles of less than 15 ns are required to set the lock
detect. It stays set high until a phase error of greater than 25 ns
is detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, this output is high with narrow,
low going pulses.
DV_DD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
CONTROL
MUXOUT
Figure 14. MUXOUT Circuit
DGND
INPUT SHIFT REGISTER
The ADF4108 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the 2 LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5.
Figure 15 shows a summary of how the latches are
programmed.
Table 5. C2 and C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
R counter
0
1
N counter (A and B)
1
0
Function latch (including prescaler)
1
1
Initialization latch
Rev. B | Page 10 of 20