EVAL-ADF4108EBZ1 Datasheet, PDF (2/20 Pages) Analog Devices – PLL Frequency Synthesizer

ADF4108
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ........................................................................ 9
Reference Input Stage................................................................... 9
RF Input Stage............................................................................... 9
Prescaler (P/P + 1)........................................................................ 9
A and B Counters ......................................................................... 9
R Counter ...................................................................................... 9
REVISION HISTORY
9/11—Rev. A to Rev. B
Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter
and Endnote 9, Table 1..................................................................... 4
Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 10,
Table 1 ................................................................................................ 4
Changes to Figure 3 and Table 4..................................................... 7
Updated Outline Dimensions ....................................................... 20
12/07—Rev. 0 to Rev. A
Removed TSSOP Package..................................................Universal
Changes to Features.......................................................................... 1
Changes to Table 1 Endnote 10 and Endnote 11.......................... 4
Changes to Table 3............................................................................ 6
Deleted Figure 3................................................................................ 7
Changes to Table 4............................................................................ 7
Changes to Figure 10 and Figure 11............................................... 8
Updated Outline Dimensions ....................................................... 20
Deleted Figure 24............................................................................ 20
Changes to Ordering Guide .......................................................... 20
4/06—Revision 0: Initial Version
Data Sheet
Phase Frequency Detector and Charge Pump........................ 10
MUXOUT and Lock Detect...................................................... 10
Input Shift Register .................................................................... 10
Latch Summary........................................................................... 11
Reference Counter Latch Map.................................................. 12
AB Counter Latch Map ............................................................. 13
Function Latch Map................................................................... 14
Initialization Latch Map ............................................................ 15
Function Latch............................................................................ 16
Initialization Latch ..................................................................... 17
Power Supply Considerations................................................... 17
Interfacing ....................................................................................... 18
ADuC812 Interface .................................................................... 18
ADSP-21xx Interface ................................................................. 18
PCB Design Guidelines for Chip Scale Package......................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
Rev. B | Page 2 of 20