DAC8512 Datasheet, PDF (4/20 Pages) Analog Devices – % V, Serial Input Complete 12-Bit DAC

DAC8512
SDI
CLK
CS
LD
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t_css
t_ld1
t_csh
t_ld2
SDI
CLK
LD
CLR
FS
VOUT
ZS
t_ds
t_cl
t_dh
t_ch
t_ldw
t_s
Figure 1. Timing Diagram
t_clrw
±1 LSB
ERROR BAND
tS
CS
CLK
SDI
ESD PROTECTION DIODES TO VDD AND GND
DATA
SHIFT
REGISTER
Figure 2. Equivalent Clock Input Logic
Table I. Control-Logic Truth Table
CS² CLK² CLR LD Serial Shift Register Function
DAC Register Function
HX
LL
LH
L
↑+
↑+ L
HX
HX
HX
HX
H H No Effect
H H No Effect
H H No Effect
H H Shift-Register-Data Advanced One Bit
H H Shift-Register-Data Advanced One Bit
H ↓– No Effect
H L No Effect
L X No Effect
↑+ H No Effect
NOTES
l _{↑+ positive logic transition; ↓– negative logic transition; X = Don’t Care.}
2_{CS and CLK are interchangeable.}
3_{Returning CS HIGH avoids an additional “false clock” of serial data input.}
4_{Do not clock in serial data while LD is LOW.}
Latched
Latched
Latched
Latched
Latched
Updated with Current Shift Register Contents
Transparent
Loaded with All Zeros
Latched All Zeros
–4–
REV. A