DAC8512 Datasheet, PDF (2/20 Pages) Analog Devices – % V, Serial Input Complete 12-Bit DAC

DAC8512–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V_DD = +5.0 V ؎ 5%, –40؇C ≤ T_A ≤ +85؇C, unless otherwise noted)
Parameter
Symbol Condition
Min Typ Max Units
STATIC PERFORMANCE
Resolution
N
Relative Accuracy
INL
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
DNL
V_ZSE
V_FS
Full-Scale Tempco
TCV_FS
ANALOG OUTPUT
Output Current
Load Regulation at Full Scale
Capacitive Load
I_OUT
L_REG
C_L
LOGIC INPUTS
Logic Input Low Voltage
V_IL
Logic Input High Voltage
V_IH
Input Leakage Current
I_IL
Input Capacitance
C_IL
INTERFACE TIMING SPECIFICATIONS^{1, 4}
Clock Width High
Clock Width Low
Load Pulse Width
Data Setup
Data Hold
Clear Pulse Width
Load Setup
Load Hold
Select
Deselect
t_CH
t_CL
t_LDW
t_DS
t_DH
t_CLRW
t_LD1
t_LD2
t_CSS
t_CSH
AC CHARACTERISTICS⁴
Voltage Output Settling Time t_S
DAC Glitch
Digital Feedthrough
Note 2
No Missing Codes
Data = 000_H
Data = FFF_H3
Notes 3, 4
E Grade
F Grade
E Grade
F Grade
Data = 800_H
R_L = 402 Ω to ∞, Data = 800_H
No Oscillation⁴
To ± 1 LSB of Final Value⁵
12
–1
–2
–1
4.087
4.079
±5
2.4
30
30
20
15
15
30
15
10
30
20
± 1/4
± 3/4
± 3/4
+1/2
4.095
4.095
16
+1
+2
+1
+3
4.103
4.111
Bits
LSB
LSB
LSB
LSB
V
V
ppm/°C
±7
mA
1
3
LSB
500
pF
0.8 V
V
10 µA
10 pF
10
ns
10
ns
ns
10
ns
5
ns
20
ns
ns
ns
ns
ns
16
µs
15
nV s
15
nV s
SUPPLY CHARACTERISTICS
Positive Supply Current
I_DD
Power Dissipation
P_DISS
Power Supply Sensitivity
PSS
V_IH = 2.4 V, V_IL = 0.8 V, No Load
V_DD = 5 V, V_IL = 0 V, No Load
V_IH = 2.4 V, V_IL = 0.8 V, No Load
V_DD = 5 V, V_IL = 0 V, No Load
∆V_DD = ± 5%
1.5
0.5
7.5
2.5
0.002
2.5
1
12.5
5
0.004
mA
mA
mW
mW
%/%
NOTES
1_{All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.}
2_{1 LSB = 1 mV for 0 V to +4.095 V output range.}
3_{Includes internal voltage reference error.}
4_{These parameters are guaranteed by design and not subject to production testing.}
5_{The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in}
this 6 LSB region.
Specifications subject to change without notice.
–2–
REV. A