ADSP-21362 Datasheet, PDF (4/52 Pages) Analog Devices – SHARC Processor

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
GENERAL DESCRIPTION
The ADSP-2136x SHARC processor is a member of the SIMD
SHARC family of DSPs that feature Analog Devices’ Super Har-
vard Architecture. The processor is source code-compatible
with the ADSP-2126x and ADSP-2116x DSPs, as well as with
first generation ADSP-2106x SHARC processors in SISD (sin-
gle-instruction, single-data) mode. The ADSP-2136x is a
32-bit/40-bit floating-point processor optimized for high
performance automotive audio applications with a large on-
chip SRAM and ROM, multiple internal buses to eliminate I/O
bottlenecks, and an innovative digital audio interface (DAI).
As shown in the functional block diagram on Page 1, the
ADSP-2136x uses two computational units to deliver a signifi-
cant performance increase over the previous SHARC processors
on a range of signal processing algorithms. Fabricated in a state-
of-the-art, high speed, CMOS process, the ADSP-2136x proces-
sor achieves an instruction cycle time of 3.0 ns at 333 MHz.
With its SIMD computational hardware, the ADSP-2136x can
perform two GFLOPS running at 333 MHz.
Table 2 shows the features of the individual product offerings
and Table 1 shows performance benchmarks for the processors
running at 333 MHz.
Table 1. Benchmarks (at 333 MHz)
Benchmark Algorithm
Speed
(at 333 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs
FIR Filter (per tap)¹
1.5 ns
IIR Filter (per biquad)¹
6.0 ns
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
13.5 ns
23.9 ns
Divide (y/x)
10.5 ns
Inverse Square Root
16.3 ns
1 _{Assumes two files in multichannel SIMD mode}
The ADSP-2136x continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram on Page 1, illustrates the following architec-
tural features:
• Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• Three programmable interval timers with PWM genera-
tion, PWM capture/pulse width measurement, and
external event counter capabilities
• On-chip SRAM (3M bit)
• On-chip ROM (4M bit)
• 8-bit or 16-bit parallel port that supports interfaces to off-
chip memory peripherals
• JTAG test access port
Table 2. ADSP-2136x SHARC Processor Family Features
Feature
RAM
3M bit 3M bit 3M bit 3M bit 3M bit
ROM
4M bit 4M bit 4M bit 4M bit 4M bit
Audio
No
No
Decoders in
ROM¹
No
Yes
Yes
Pulse Width Yes Yes
Modulation
Yes
Yes
Yes
S/PDIF
DTCP²
Yes No
Yes No
Yes
Yes
Yes
No
Yes
No
SRC
128 dB No SRC 140 dB 128 dB 128 dB
Performance
1 _{Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,}
DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like Bass
management, delay, speaker equalization, graphic equalization, and more.
Decoder/post-processor algorithm combination support varies depending upon
the chip version and the system configurations. Please visit www.analog.com for
complete information.
2 _{The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission}
Content Protection protocol, a proprietary security protocol. Contact your
Analog Devices sales office for more information.
The block diagram on Page 7 illustrates the following architec-
tural features:
• DMA controller
• Six full duplex serial ports
• Two SPI-compatible interface ports—primary on dedi-
cated pins, secondary on DAI pins
• Digital audio interface that includes two precision clock
generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample
rate converter, DTCP cipher, six serial ports, eight serial
interfaces, a 20-bit parallel input port, 10 interrupts, six flag
outputs, six flag inputs, three timers, and a flexible signal
routing unit (SRU)
Figure 2 shows a sample SPORT configuration using the preci-
sion clock generators to interface with an I²S ADC and an I²S
DAC with a much lower jitter clock than the serial port would
generate itself. Many other SRU configurations are possible.
Rev. A | Page 4 of 52 | December 2006