ADSP-21362 Datasheet, PDF (32/52 Pages) Analog Devices – SHARC Processor

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 28. Serial Ports—Enable and Three-State
Parameter
Min
Switching Characteristics
t_DDTEN¹
Data Enable from External Transmit SCLK
2
t_DDTTE¹
Data Disable from External Transmit SCLK
t_DDTIN¹
Data Enable from Internal Transmit SCLK
–1
1 _{Referenced to drive edge.}
Table 29. Serial Ports—External Late Frame Sync
Parameter
Min
Switching Characteristics
t_DDTLFSE¹
Data Delay from Late External Transmit FS or External Receive
FS with MCE = 1, MFD = 0
t_DDTENFS¹
Data Enable for MCE = 1, MFD = 0
0.5
1 _{The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.}
Max
7
Max
9
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE
SAMPLE DRIVE
t_SFSE/I
t_HFSE/I
t_DDTENFS
t_HDTE/I
1ST BIT
t_DDTE/I
2ND BIT
t_DDTLFSE
LATE EXTERNAL TRANSMIT FS
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE
SAMPLE DRIVE
t_SFSE/I
t_HFSE/I
t_DDTENFS
t_HDTE/I
1ST BIT
t_DDTE/I
2ND BIT
t_DDTLFSE
NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
Figure 22. External Late Frame Sync¹
1 _{This figure reflects changes made to support left-justified sample pair mode.}
Unit
ns
ns
ns
Unit
ns
ns
Rev. A | Page 32 of 52 | December 2006