ADSP-21362 Datasheet, PDF (29/52 Pages) Analog Devices – SHARC Processor

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-2136x is accessing external memory space.
Table 24. 8-Bit Memory Write Cycle
Parameter
Switching Characteristics
t_ALEW
t_ADAS¹
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
t_ALERW
ALE Deasserted to Write Asserted
t_RWALE
Write Deasserted to ALE Asserted
t_WRH
t_ADAH¹
Delay Between WR Rising Edge to Next WR Falling Edge
AD15–0 Address Hold After ALE Deasserted
t_WW
WR Pulse Width
t_ADWL
AD15–8 Address to WR Low
t_ADWH
AD15–8 Address Hold After WR High
t_DWS
AD7–0 Data Setup Before WR High
t_DWH
AD7–0 Data Hold After WR High
t_DAWH
AD15–8 Address to WR High
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × t_PCLK.
H = t_PCLK (if a hold cycle is specified, else H = 0)
F = 7 × t_PCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × t_PCLK.
t_PCLK = (peripheral) clock period = 2 × t_CCLK
1 _{On reset, ALE is an active high cycle. However, it can be configured by software to be active low.}
Min
2 × t_PCLK – 2.0
t_PCLK – 2.8
2 × t_PCLK – 3.8
H + 0.5
F + H + t_PCLK – 2.3
t_PCLK – 0.5
D – F – 2.0
t_PCLK – 2.8
H
D – F + t_PCLK – 4.0
H
D – F + t_PCLK – 4.0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE
WR
RD
AD15-8
AD7-0
t_ALEW
t_ALERW
t_WW
t_RWALE
t_ADWL
t_DAWH
t_WRH
t_ADAS
t_ADAH
VALID
ADDRESS
VALID ADDRESS
VALID
ADDRESS
t_DWS
VALID DATA
t_ADWH
VALID ADDRESS
t_DWH
VALID DATA
NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR
BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY
WRITES IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION.
Figure 20. Write Cycle for 8-Bit Memory Timing
Rev. A | Page 29 of 52 | December 2006