ADSP-21362 Datasheet, PDF (1/52 Pages) Analog Devices – SHARC Processor

a
SHARC^® Processor
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SUMMARY
High performance, 32-bit/40-bit, floating-point processor
optimized for high performance processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM
Code compatible with all other members of the SHARC family
The ADSP-2136x processors are available with a 333 MHz
core instruction rate and unique peripherals such as the digi-
tal audio interface, S/PDIF transceiver, DTCP (digital
transmission content protection protocol), serial ports,
8-channel asynchronous sample rate converter, precision
clock generators, and more. For complete ordering informa-
tion, see Ordering Guide on Page 52.
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32-BIT ؋ 48-BIT
DAG1
8؋4؋32
DAG2
8؋4؋32
PROGRAM
SEQUENCER
BLOCK 0
SRAM
1M BIT ROM
2M BIT
4 BLOCKS OF ON-CHIP MEMORY
BLOCK 1
BLOCK 2
SRAM
1M BIT ROM
2M BIT
SRAM
0.5M BIT
BLOCK 3
SRAM
0.5M BIT
ADDR DATA
ADDR DATA ADDR DATA ADDR DATA
PM ADDRESS BUS
32
DM ADDRESS BUS 32
PM DATA BUS
64
DM DATA BUS 64
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
PX REGISTER
6
JTAG TEST AND EMULATION
S
IOA
IOD
IOA
IOD
IOA
IOD
IOP REGISTERS
(MEMORY MAPPED)
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
DTCP
I/O PROCESSOR
AND PERIPHERALS
IOA
IOD
SIGNAL
ROUTING
UNIT
Figure 1. Functional Block Diagram—Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. A
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