ADSP-21469 Datasheet, PDF (35/56 Pages) Analog Devices – SHARC Processor material that is subject to change without notice

Preliminary Technical Data
ADSP-21469/ADSP-21469W
Table 32. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
t_DDTEN¹
Data Enable from External Transmit SCLK
t_DDTTE¹
Data Disable from External Transmit SCLK
t_DDTIN¹
Data Enable from Internal Transmit SCLK
1 _{Referenced to drive edge.}
Min
Max
TBD
TBD
TBD
TBD
TBD
TBD
Table 33. Serial Ports—External Late Frame Sync
Parameter
Min
Max
Switching Characteristics
t_DDTLFSE¹
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
TBD
TBD
t_DDTENFS¹
Data Enable for MCE = 1, MFD = 0
TBD
TBD
1 _{The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.}
Unit
ns
ns
ns
Unit
ns
ns
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
D RIVE
t_SFSE/I
t_HFSE/I
t_DDTENFS
t_HDTE/I
1ST BIT
t_{D DTLFSE}
t_DDTE/I
2ND BIT
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DA I_P 20-1
(DATA CHANNEL A/B)
LATE EXTERNAL TRANSMIT FS
DRIVE
SAMPLE
D RIVE
t_SFSE/I
t_HFSE/I
t_DDTENFS
t_HDTE/I
1ST BIT
t_DDTE/I
2ND BIT
t_DDTLFSE
NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
THE CHARACTERIZED AC SPORT TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES
ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH SAU.
Figure 22. External Late Frame Sync¹
1 _{This figure reflects changes made to support left-justified sample pair mode.}
Rev. PrB | Page 35 of 56 | November 2008