ADSP-21469 Datasheet, PDF (16/56 Pages) Analog Devices – SHARC Processor material that is subject to change without notice

ADSP-21469/ADSP-21469W
SPECIFICATIONS
Preliminary Technical Data
OPERATING CONDITIONS
Parameter¹
Description
Min
Max
Unit
V_{DD_INT}
V_{DD_EXT}
V_{DD_DDR2}³
V_REF
V_IH⁴
V_IL⁴
V_{IH_CLKIN}⁵
V_{IL_CLKIN}⁵
V_{IL_DDR2}
V_{IH_DDR2}
T_JUNCTION
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
DDR2 Controller Supply Voltage
DDR2 Reference Voltage
High Level Input Voltage @ V_{DD_EXT} = max
Low Level Input Voltage @ V_{DD_EXT} = min
High Level Input Voltage @ V_{DD_EXT} = max
Low Level Input Voltage @ V_{DD_EXT} = min
Low Level Input Voltage
High Level Input Voltage
Junction Temperature 208-Lead PBGA @ T_AMBIENT 08C to +708C
TBD²
3.14
1.71
0.84
2.0
-0.3
TBD
TBD
-0.3
V_REF + 0.13
0
TBD²
V
3.46
V
1.89
V
0.96
V
3.6
V
0.8
V
TBD
V
TBD
V
V_REF - 0.12
V
V_{DD_DDR2} + 0.3 V
125
C
1 _{Specifications subject to change without notice.}
2 _{The expected value is 1.1V and initial customer designs should design with a programmable regulator that can be adjusted from 0.95V to 1.15V +/-50mV}
3 _{Applies to DDR2 signals.}
4 _{Applies to input and bidirectional pins: AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOTCFGx, CLKCFGx, CLKOUT (RUNRSTIN), RESET,}
TCK, TMS, TDI, TRST.
5 _{Applies to input pin CLKIN.}
Rev. PrB | Page 16 of 56 | November 2008