ADSP-21469 Datasheet, PDF (29/56 Pages) Analog Devices – SHARC Processor material that is subject to change without notice

Preliminary Technical Data
ADSP-21469/ADSP-21469W
DDR2 SDRAM Write Cycle Timing
Table 25. DDR2 SDRAM Write Cycle Timing, V_DD-DDR2 nominal 1.8V
Parameter
Switching Characteristics
TBD
Symbol
TBD
TBD
Figure 17. DDR2 SDRAM Controller Output AC Timing
Minimum
TBD
Maximum Unit
TBD
TBD
Rev. PrB | Page 29 of 56 | November 2008