ADSP-21469 Datasheet, PDF (1/56 Pages) Analog Devices – SHARC Processor material that is subject to change without notice

Preliminary Technical Data
SUMMARY
Note: This datasheet is preliminary. This document contains
material that is subject to change without notice.
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—5 Mbits of on-chip RAM
SHARC Processor
ADSP-21469/ADSP-21469W
Code compatible with all other members of the SHARC family
The ADSP-21469 is available with a 450 MHz core instruction
rate with unique audiocentric peripherals such as the digi-
tal applications interface, serial ports, precision clock
generators, S/PDIF transceiver, asynchronous sample rate
converters, input data port, and more.
For complete ordering information, see Ordering Guide on
Page 56.
PLL
THERMAL
DIODE
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
DAG1
8 x 4 x 32
DAG2
8 x 4 x 32
PROGRAM
SEQUENCER
PM ADDRESS BUS ₃₂
DM ADDRESS BUS
32
PM DATA BUS 64
DM DATA BUS ⁶⁴
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
PX REGISTER
4 BLOCKS OF
ON-CHIP MEMORY
5M BIT RAM
JTAG TEST & EMULATION
EXTERNAL PORT
8 DATA
ADDR
32
DATA
48
IOA(19)
ASYNCHRONOUS
MEMORY
INTERFACE
(AMI)
DDR2 DRAM
CONTROLLER
IOD(32)
24 ADDRESS
3
7
16
19
FLAGS
PWM
AMI CONTROL
DDR2 CONTROL
DATA
ADDRESS
IOP REGISTER CONTROL
STATUS, & DATA BUFFERS
DMA
ARBITER
ACCELERATORS
FFT FIR IIR
LINK
20
PORTS
4
GPIO
IRQ/FLAGS
S
PRECISION CLOCK
GENERATORS (4)
S/PDIF (RX/TX)
SERIAL PORTS (8)
INPUT DATA PORT/
PDAP
ASRC
DAI PINS (20)
DIGITAL APPLICATIONS INTERFACE
20
Figure 1. Functional Block Diagram
SPI PORT (2)
TWO WIRE
INTERFACE
GPIO
UART
DPI PINS (14)
GP TIMERS (2)
DIGITAL PERIPHERAL INTERFACE
14
I/O PROCESSOR
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Rev. PrB
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