DAC8562 Datasheet, PDF (3/16 Pages) Analog Devices – +5 Volt, Parallel Input Complete 12-Bit DAC

DAC8562
WAFER TEST LIMITS (@ VDD = +5.0 V ؎ 5%, RL = No Load, TA = +25؇C, applies to part number DAC8562GBC only,
unless otherwise noted)
Parameter
Symbol Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
Reference Output Voltage
INL
DNL
V_ZSE
V_FS
V_REF
No Missing Codes
Data = 000_H
Data = FFF_H
–1
± 3/4
+1
LSB
–1
± 3/4
+1
LSB
+1/2
+3
LSB
4.085
4.095
4.105
V
2.490
2.500
2.510
V
LOGIC INPUTS
Logic Input Low Voltage
V_IL
Logic Input High Voltage
V_IH
Input Leakage Current
I_IL
0.8
V
2.4
V
10
µA
SUPPLY CHARACTERISTICS
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
I_DD
P_DISS
PSS
V_IH = 2.4 V, V_IL = 0.8 V
V_IL = 0 V, V_DD = +5 V
V_IH = 2.4 V, V_IL = 0.8 V
V_IL = 0 V, V_DD = +5 V
∆V_DD = ± 5%
3
6
mA
0.6
1
mA
15
30
mW
3
5
mW
0.002
0.004
%/%
NOTE
1_{Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed}
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS*
V_DD to DGND and AGND . . . . . . . . . . . . . . . . –0.3 V, +10 V
Logic Inputs to DGND . . . . . . . . . . . . . . . –0.3 V, V_DD + 0.3 V
V_OUT to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD + 0.3 V
V_REFOUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V, V_DD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD
I_OUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . . (T_J max – T_A)/␪_JA
Thermal Resistance ␪_JA
20-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . . 74°C/W
20-Lead SOIC Package (S) . . . . . . . . . . . . . . . . . . . 89°C/W
Maximum Junction Temperature (T_J max) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1
CE
0
1
DB_11–0
0
1
CLR
0
FS
V_OUT
ZS
t_CEW
t_DS
t_DH
DATA VALID
t_CLRW
±1 LSB
ERROR BAND
t_S
t_S
Figure 2. Timing Diagram
Table I. Control Logic Truth Table
CE
CLR
DAC Register Function
H
H
L
H
↑+
H
X
L
H
↑+
Latched
Transparent
Latched with New Data
Loaded with All Zeros
Latched All Zeros
↑ + Positive Logic Transition; X Don't Care.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic
fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be
discharged to the destination socket before devices are inserted.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE