DAC8562 Datasheet, PDF (14/16 Pages) Analog Devices – +5 Volt, Parallel Input Complete 12-Bit DAC

DAC8562
Decoding Multiple DAC8562s
The CE function of the DAC8562 can be used in applications
to decode a number of DACs. In this application, all DACs re-
ceive the same input data; however, only one of the DACs’ CE
input is asserted to transfer its parallel input register contents
into the DAC. In this circuit, shown in Figure 40, the CE tim-
ing is generated by a 74HC139 decoder and should follow the
DAC8562’s standard timing requirements. To prevent timing
errors, the 74HC139 should not be activated by its ENABLE
input while the coded address inputs are changing. A simple
timing circuit, R1 and C1, connected to the DACs’ CLR pins
resets all DAC outputs to zero during power-up.
MICROPROCESSOR INTERFACING
DAC-8562–MC68HC11 INTERFACE
The circuit illustrated in Figure 41 shows a parallel interface be-
tween the DAC8562 and a popular 8-bit microcontroller, the
M68HC11, which is configured in a single-chip operating
mode. The interface circuit consists of a pair of 74ACT11373
transparent latches and an inverter. The data is loaded into the
latches in two 8-bit bytes; the first byte contains the four most
significant bits, and the lower 8 bits are in the second byte. Data
is taken from the microcontroller’s port B output lines, and
three interface control lines, CLR, CE, and MSB/LSB, are con-
trolled by the M68HC11's PC2, PC1, and PC0 output lines, re-
spectively. To transfer data into the DAC, PC0 is set, enabling
U1’s outputs. The first data byte is loaded into U1 where the
four least significant bits of the byte are connected to
MSB–DB8. PC0 is then cleared; this latches U1’s inputs and
enables U2’s outputs. U2s outputs now become DB7–DB0.
The DAC output is updated with the contents of U1 and U2
when PC1 is cleared. The DAC’s CLR input, controlled by the
M68HC11’s PC2 output line, provides an asynchronous clear
function that sets the DAC’s output to zero. Included in this sec-
tion is the source code for operating the DAC-8562–M68HC11
interface.
+5V
DATA
C1
0.1µF
R1
1k Ω
15
V_OUT1
13
16 _DAC-8562
#1
+5V
74HC139
0.1µF ¹⁶
V_CC
4
1Y0
ENABLE
1
1G
5
1Y1
CODED
ADDRESS
2 _1A
3 _1B
6
1Y2
7
1Y3
+5V
15 _2G
1kΩ ₁₄
2A
12
2Y0
NC
11
2Y1
NC
13
2B
10
2Y2
NC
8
GND
9
2Y3
NC
15
V_OUT2
13
16 _DAC-8562
#2
15
V_OUT3
13
16 _DAC-8562
#3
15
V_OUT4
13
16 _DAC-8562
#4
Figure 40. Decoding Multiple DAC8562s Using the CE Pin
*M6BHC11
PC2
CLR
PC1
CE
74HC04
MSB/ LSB 1
2
PC0
74ACT11373
13
C
23
1D
1
1Q
22
2D
21
3D
20
4D
1
U1
5D
16
6D
15
7D
14
8D
24
OC
2
2Q
3
3Q
4
4Q
9
5Q
10
6Q
11
7Q
12
8Q
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
74ACT11373
13
C
23
1D
22
2D
21
3D
20
4D
1
U2
5D
16
6D
15
7D
14
8D
24
OC
1
1Q
2
2Q
3
3Q
4
4Q
9
5Q
10
6Q
11
7Q ₁₂
8Q
NC
NC
NC
NC
PC2
PC1
*DAC-8562
15
CLR
16
CE
9
MSB
8
DB10
7
DB9
6
U3
DB8
5
DB7
4
13
V_OUT
DB6
3
DB5
2
DB4
1
DB3
19
DB2
18
DB1
17
LSB
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. DAC8562 to MC68HC11 Interface
–14–
REV. A