DAC8420_07 Datasheet, PDF (21/24 Pages) Analog Devices – Quad 12-Bit Serial Voltage Output DAC

DAC8420
DAC8420 TO M68HC11 INTERFACE ASSEMBLY PROGRAM
* M68HC11 Register Definitions
* Initialize SPI Interface
PORTC EQU $1003 Port C control register
LDAA #$5F
* “0,0,0,0;0,CLSEL,CLR,CS”
STAA SPCR SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32
DDRC EQU $1007 Port C data direction
* Call update subroutine
PORTD EQU $1008 Port D data register
BSR UPDATE Xfer 2 8-bit words to DAC-8420
* “0,0,LD,SCLK;SDI,0,0,0”
JMP $E000 Restart BUFFALO
DDRD EQU $1009 Port D data direction
* Subroutine UPDATE
SPCR EQU $1028 SPI control register
UPDATE PSHX Save registers X, Y, and A
* “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0”
PSHY
SPSR EQU $1029 SPI status register
PSHA
* “SPIF,WCOL,0,MODF;0,0,0,0”
* Enter Contents of SDI1 Data Register (DAC# and 4 MSBs)
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter
LDAA #$80 1,0,0,0;0,0,0,0
*
STAA SDI1 SDI1 is set to 80 (Hex)
* SDI RAM variables: SDI1 is encoded from 0 (Hex) to CF (Hex)
* Enter Contents of SDI2 Data Register
* To select: DAC A – Set SDI1 to $0X
LDAA #$00 0,0,0,0;0,0,0,0
DAC B – Set SDI1 to $4X
STAA SDI2 SDI2 is set to 00 (Hex)
DAC C – Set SDI1 to $8X
LDX #SDI1 Stack pointer at 1st byte to send via SDI
DAC D – Set SDI1 to $CX
LDY #$1000 Stack pointer at on-chip registers
SDI2 is encoded from 00 (Hex) to FF (Hex)
* Clear DAC output to zero
* DAC requires two 8-bit loads – Address + 12 bits
BCLR PORTC,Y $02 Assert CLR
SDI1 EQU $00 SDI packed byte 1 “A1,A0,0,0;MSB,DB10,DB9,DB8”
BSET PORTC,Y $02 Deassert CLR
SDI2 EQU $01 SDI packed byte 2
* Get DAC ready for data input
“DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0”
BCLR PORTC,Y $01 Assert CS
* Main Program
TFRLP LDAA 0,X Get a byte to transfer via SPI
ORG $C000 Start of user’s RAM in EVB
STAA SPDR Write SDI data reg to start xfer
INIT LDS #$CFFF Top of C page RAM
WAIT LDAA SPSR Loop to wait for SPIF
* Initialize Port C Outputs
BPL WAIT SPIF is the MSB of SPSR
LDAA #$07 0,0,0,0;0,1,1,1
*
(when SPIF is set, SPSR is negated)
* CLSEL-Hi, CLR-Hi, CS-Hi
INX
Increment counter to next byte for xfer
* To reset DAC to ZERO-SCALE, set CLSEL-Lo ($03)
CPX #SDI2+ 1 Are we done yet ?
* To reset DAC to MID-SCALE, set CLSEL-Hi ($07)
BNE TFRLP If not, xfer the second byte
STAA PORTC Initialize Port C Outputs
* Update DAC output with contents of DAC register
LDAA #$07 0,0,0,0;0,1,1,1
BCLR PORTD,Y 520 Assert LD
STAA DDRC CLSEL, CLR, and CS are now enabled as outputs
BSET PORTD,Y $20 Latch DAC register
* Initialize Port D Outputs
BSET PORTC,Y $01 De-assert CS
LDAA #$30 0,0,1,1;0,0,0,0
PULA When done, restore registers X, Y & A
* LD-Hi,SCLK-Hi,SDI-Lo
PULY
STAA PORTD Initialize Port D Outputs
PULX
LDAA #$38 0,0,1,1;1,0,0,0
RTS ** Return to Main Program **
STAA DDRD LD,SCLK, and SDI are now enabled as outputs
Rev. B | Page 21 of 24